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dual low power , 8- /10 - /12 - /14 - bit txdac digital - to - analog conve rters data sheet ad9114 / ad9115 / ad9116 / ad9117 rev. d document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any in fringements of patents or other rights of third parties that may result from its use. specifica tions subject to change without notice. no license is granted by implication or otherwise under any patent or patent right s of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 ? 2008 ? 2017 analog devices, inc. all rights reserved. technical support www.analog.com features power dissipation @ 3.3 v , 20 ma out put 191 mw @ 10 msps 232 mw @ 125 msps sleep mode: <3 mw @ 3.3 v supply voltage : 1.8 v to 3.3 v sfdr to nyquist 86 dbc @ 1 mhz output 8 5 dbc @ 10 mhz output ad 9117 nsd @ 1 mhz out put , 125 ms ps , 20 ma : ?162 dbc / hz diff erential current outputs: 2 ma to 20 ma 2 on - chip auxiliary dacs cmos inputs with single - port operation output common mode: adjustable 0 v to 1.2 v small footprint 40 - lead lfcsp rohs - compliant package applications wireless infrastructures picocell, femtocell base stations medical instrumentation ultrasound transducer excitation portable instrumentation signal generators, arbitrary waveform generators general description the ad 9114/ad9115/ad9116/ad9117 are pin - compatible dual, 8 - /10 - /12 - /14 - bit, low power digital - to - analog converters ( dacs ) that provide a sample rate of 125 msps. these txdac? converters are optimized for the transmit signal path of commu - nication systems. all the devices share the same interface, package , and pinout, providing an upward or downward component selection path based on performance, resolution, and cost. the ad 9114/ad9115/ad9116/ad9117 offer exceptional ac and dc performance and support update rates up to 125 msps. the flexible pow er supply operating range of 1.8 v to 3.3 v and low power dissipation of the ad 9114/ad9115/ad9116/ad9117 make them well suited for portable and low power applications. product highlights 1. low power. dacs operate on a single 1.8 v to 3.3 v supply ; t ot al power consumption reduces to 225 mw at 1 00 msps. sleep and power - down modes are provided for low power idle periods. 2. cmos clock input. high speed, single- ended cmos clock input supports a 125 msps conversion rate. 3. easy interfacing to other components. adjustable output common mode from 0 v to 1.2 v allows for easy interfacing to other components that accept common - mode levels greater than 0 v.
ad9114/ad9115/ad9116/ad9117 data sheet rev. d | page 2 of 52 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 general description ......................................................................... 1 product highlights ........................................................................... 1 revisi on history ............................................................................... 3 functional block diagram .............................................................. 4 specifications ..................................................................................... 5 dc spec ifications ......................................................................... 5 digital specifications ................................................................... 7 ac specifications .......................................................................... 8 absolu te maximum ratings ............................................................ 9 thermal resistance ...................................................................... 9 esd caution .................................................................................. 9 pin conf igurations and function descriptions ......................... 10 typical performance characteristics ........................................... 18 terminology .................................................................................... 31 theory of operation ...................................................................... 32 serial peripheral interface (spi) ................................................... 33 general operation of the serial interf ace ............................... 33 instruction byte .......................................................................... 33 serial interface port pin descriptions ..................................... 33 msb/lsb transfers ..................................................................... 34 serial port operation ................................................................. 34 pin mode ..................................................................................... 34 s pi register map ............................................................................. 35 spi register descriptions .............................................................. 36 digital interface operation ........................................................... 40 digital data latching and retimer section ............................ 41 estimating the overall dac pipeline delay ........................... 42 reference operation .................................................................. 43 reference control amplifier .................................................... 43 dac transfer function ............................................................. 43 analog o utput ............................................................................ 44 self- calibration ........................................................................... 44 coarse gain adjustment ........................................................... 45 using the internal termination resistors ............................... 46 applications information .............................................................. 47 output configurations .............................................................. 47 differential coupling using a transformer ............................... 47 single - ended buffered output using an op amp ................ 47 differentia l buffered output using an op amp .................. 48 auxiliary dacs ........................................................................... 48 dac - to - modulator interfacing ................................................ 49 correcting for nonideal performance of quadrature modulators on the if - to - rf conversion ................................ 49 i/q channel gain matching ..................................................... 49 lo feedthrough compensation .............................................. 50 results of gain and offset correction .................................... 50 outline dimensions ....................................................................... 51 ordering guide .......................................................................... 52
data sheet ad9114/ad9115/ad9116/ad9117 rev. d | page 3 of 52 revision history 12/ 2017 ? rev. c to rev. d change s to f igure 94 ...................................................................... 41 changes to estimating the overall dac pipeline delay section .. 42 updated outline dimensions ........................................................ 51 changes to ordering guide ........................................................... 52 3/ 2013 ? rev. b to rev. c change to feature s section .............................................................. 1 change to endnote 1, table 1 .......................................................... 6 changes to figure 86 and figure 88 ............................................. 34 change t o table 13 .......................................................................... 35 change to version register description, table 14 ..................... 39 changes to table 17 and re ference control amplifier section .............................................................................................. 43 changes to using the internal termination resistors section .............................................................................................. 46 changes to single - ended buffered output using an op amp section .............................................................................................. 47 changes to differential buffered output using an op amp section .............................................................................................. 48 updated outline dime nsions ........................................................ 51 5/ 2012 ? rev. a to rev. b changes to table 1 ............................................................................ 5 changes to table 2 ............................................................................ 7 changes to table 3 and table 4 ....................................................... 8 changes to theory of operation section .................................... 32 changes to sclk serial clock section ..................................... 33 changes to pin mode section ........................................................ 34 changes to table 14 ........................................................................ 37 changes to self- calibration section ............................................. 44 deleted modifying the evaluation board to use the adl5370 on - board quadrature modulator section .......................................... 51 deleted evaluation board schematics and artwork section and figure 111 to figure 133, renumbered sequentially .................. 52 updated outline dimensions ........................................................ 51 changes to ordering guide ........................................................... 52 deleted bill of materials section and table 18 ............................ 75 3/ 20 09? rev. 0 to rev. a changes to product title and general description section ....... 1 changes to figure 1 .......................................................................... 4 changed i outfs = 2 ma to i x outfs = 20 ma .................................... 5 changes to t able 1 ............................................................................ 6 changed i outfs = 2 ma to i x outfs = 20 ma .................................... 7 changes to table 2 ............................................................................ 7 changed dvddio = 1.8 v to dvddio = 3.3 v , table 3 and cvdd = 3.3 v to cvdd = 1.8 v , table 4 ..................................... 8 change s to table 5 and table 6 ....................................................... 9 changes to table 7 .......................................................................... 10 changes to table 8 .......................................................................... 12 changes to table 9 .......................................................................... 14 changes to table 10 ........................................................................ 16 changes to typical performance characteristics section ......... 18 changes to theory of operation section and figure 84 ........... 32 added figure 85 to figure 88; renumbered sequentially ......... 34 changes to table 13 ........................................................................ 35 changes to table 14 ........................................................................ 36 chang es to digital interface operation section and figure 89, figure 90, figure 91, figure 92, and figure 93 ............................ 40 changes to figure 94, digital data latching section, and retimer section ............................................................................... 41 added reference operation section, reference control amplifier section, d ac transfer function section, figure 96, and table 17 ..................................................................................... 43 added analog output section ...................................................... 44 changes to auxiliary dacs section ............................................. 48 changes to dac to modulator interfacing section, figure 107, and figure 108 ................................................................................. 49 adde d figure 1 11 to figure 1 33 .................................................... 52 added table 18 ................................................................................ 75 8/ 2008 ? revision 0: initial version
ad9114/ad9115/ad9116/ad9117 data sheet rev. d | page 4 of 52 functional block dia gram i dac q dac aux1dac aux2dac band gap clock dist 10k? qr set 2k? ir set 2k? i ref 100a ir cm 60? to 260? qr cm 60? to 260? 62.5? 62.5? 62.5? 62.5? spi interface 1 into 2 interleaved data interface i data q data 1.8v ldo 1v ad9117 rlin ioutn ioutp rlip avdd avss rlqp qoutp qoutn rlqn db11db10 db9db8 dvddio dvss dvdd db7db6 db5 db12 db13 (msb) cs/pwrdn sdio/format sclk/clkmd reset/pinmd refio fsadjq/auxq fsadji/auxi cmli db4db3 db2 db1 (lsb) db0 dclkio cvdd clkin cvss cmlq 07466-001 figure 1.
data sheet ad9114/ad9115/ad9116/ad9117 rev. d | page 5 of 52 specifications dc specifications t min to t max , avdd = 3.3 v, dvdd = 1 .8 v, dvddio = 3.3 v, cvdd = 3.3 v, i x outfs = 2 0 ma, maximum sample rate, unless ot herwise noted. table 1 . parameter ad 9114 ad 9115 ad 9116 ad 9117 unit min typ max min typ max min typ max min typ max resolution 8 10 12 14 bits accuracy, avdd = dvddio = cvdd = 3.3 v differential nonlinea rity (dnl) precalibration 0.02 0.06 0.4 1.4 lsb postcalibration 0.0 2 0.04 0. 2 0.6 lsb integral nonlinearity (inl) precalibration 0.03 0.19 0.68 1.2 lsb postcalibration 0.03 0.07 0.4 2 0.6 lsb accuracy , a vdd = dvddio =cvdd = 1.8 v differential nonlinearity (dnl) precalibration 0.02 0.0 8 0.5 1.8 lsb postcalibration 0.0 1 0.0 6 0.2 1.0 lsb integral nonlinearity (inl) precalibration 0.0 4 0. 2 0.5 1.8 lsb postcalibration 0.0 2 0.1 0.3 1.1 lsb main dac outputs offset error ?1 +1 ?1 +1 ?1 +1 ?1 +1 mv gain error internal reference ?2 +2 ?2 +2 ?2 +2 ?2 +2 % of fsr full - scale o utput current 1 av dd = 3.3 v 2 8 20 2 8 20 2 8 20 2 8 20 ma av dd = 1.8 v 2 8 2 8 2 8 2 8 ma output common - mode level (8 ma cml x pin) ? 0.5 0 + 1.2 ? 0.5 0 + 1.2 ? 0.5 0 + 1.2 ? 0.5 0 + 1.2 v output compliance r ange avdd = 3.3 v , 8 ma output common mode level = ?0.5 ?0.9 ?0.1 ?0.9 ?0.1 ?0.9 ?0.1 ?0.9 ?0.1 v common mode level = 0 ?0.4 +0.4 ?0.4 +0.4 ?0.4 +0.4 ?0.4 +0.4 v common mode level = + 1.2 0.8 1.5 0.8 1.5 0.8 1.5 0.8 1.5 v output resistance 200 200 200 200 m crosstalk, q dac to i dac (f out = 30 mhz) 95 95 95 95 db crosstalk, q dac to i dac (f out = 60 mhz) 76 76 76 76 db main dac temperature drift offset 0 0 0 0 ppm/c gain 40 40 40 40 ppm/c reference voltage 25 25 25 25 ppm/c
ad9114/ad9115/ad9116/ad9117 data sheet rev. d | page 6 of 52 parameter ad 9114 ad 9115 ad 9116 ad 9117 unit min typ max min typ max min typ max min typ max auxdac outputs resolution 10 10 10 10 bits full - scale output current (current sourcing mode ) 125 125 125 125 a voltage output mode output compliance range (sourcing 1 ma) v ss v dd ? 0.25 v ss v dd ? 0.25 v ss v dd ? 0.25 v ss v dd ? 0.25 v output compliance range (sinking 1 ma) v ss + 0.25 v dd v ss + 0.25 v dd v ss + 0.25 v dd v ss + 0.25 v dd v output resistance in current output mode av ss to 1 v 1 1 1 1 m auxdac monotonicit y guaranteed 10 10 10 10 bits reference output internal reference voltage 0.98 1.025 1.08 0.98 1.025 1.08 0.98 1.025 1.08 0.98 1.025 1.08 v output resistance 10 10 10 10 k reference input voltage compliance avdd = 3.3 v 0.1 1.25 0.1 1.25 0.1 1.25 0.1 1.25 v avdd = 1.8 v 0.1 1.0 0.1 1.0 0.1 1.0 0.1 1.0 v input resistance ext ernal ref erence mode 1 1 1 1 m dac matching gain matching ?1 +1 ?1 +1 ?1 +1 ?1 +1 % o f fsr analog supply voltages avdd 1.7 3.5 1.7 3.5 1.7 3.5 1.7 3.5 v cvdd 1.7 3.5 1.7 3.5 1.7 3.5 1.7 3.5 v digital supply voltages dvdd 1.7 1.9 1.7 1.9 1.7 1.9 1.7 1.9 v dvddio 1.7 3.5 1.7 3.5 1.7 3.5 1.7 3. 5 v power consumption , avdd = dvddio = cvdd = 3.3 v f dac = 125 msps, if = 12.5 mhz 220 220 220 220 mw i avdd 55 55 55 55 ma i dvdd + i dvddio 10 10 10 10 ma i cvdd 3 3 3 3 ma power - down mode with clock 8.5 8.5 8.5 8.5 mw power - down mode no clock 3 3 3 3 mw power supply rejection ratio ?0.009 ?0.009 ?0.009 ?0.009 % fsr/v power consumption , avdd = dvddio = cvdd = 1.8 v f dac = 125 msps, if = 12.5 mhz 58 58 58 58 mw i avdd 24 24 24 24 ma i dvdd + i dv d dio 8 8 8 8 ma i cvdd 2 2 2 2 ma power - down mode with clock 12 12 12 12 mw power - down mode no clock 850 850 850 850 w power supply rejection ratio ? 0.007 ?0.007 ?0.007 ?0.007 % fsr/v operating range ? 40 +25 +85 ? 40 +25 +85 ? 40 +25 +85 ? 40 +25 +85 c 1 based on a 1.6 k external resistor for 20 ma full - scale current.
data sheet ad9114/ad9115/ad9116/ad9117 rev. d | page 7 of 52 digital specificatio ns t min to t max , avdd = 3.3 v, dvdd = 1 .8 v, dvddio = 3.3 v, cvdd = 3.3 v, i xoutfs = 2 0 ma, maximum sample rate, unless otherwise noted. table 2 . parameter min typ max unit dac clock input (clkin) v ih 2.1 3 v v il 0 0.9 v maximum clock rate 125 msps serial peripheral interface maximum clock rate (sclk) 25 mhz minimum pulse width high 20 ns minimum pu lse width low 20 ns minimum sdio and to sclk setup, t ds 10 ns minimum sclk to sdio hold, t dh 5 ns maximum sclk to valid sdio, t dv 20 ns minimum sclk to invalid sdio, t dnv 5 ns input data 1.8 v q channel or dclkio falling edge s etup 0.25 ns hold 1.2 ns 1.8 v i channel or dclkio rising edge setup 0.13 ns hold 1.1 ns 3.3 v q channel or dclkio falling edge setup ? 0.2 ns hold 1.5 ns 3.3 v i channel or dclkio rising edge setup ? 0.2 ns hold 1.6 ns dvddio = 3.3 v v ih 2.1 3 v v il 0 0.9 v dvddio = 1.8 v v ih 1.2 1.8 v v il 0 0.5 v
ad9114/ad9115/ad9116/ad9117 data sheet rev. d | page 8 of 52 ac specifications t min to t max , avdd = 3.3 v, dvdd = 1.8 v, dvddio = 3.3 v, cvdd = 3.3 v, i xoutfs = 2 0 ma, maximum sample rate, unless otherwise noted. ta ble 3. parameter ad9114 ad9115 ad9116 ad9117 unit min typ max min typ max min typ max min typ max dynamic performance output settling time (t st ) to 0.1 % 11.5 11.5 11.5 11.5 ns output rise time (10% to 90 %) 0.27 0.27 0.27 0.27 ns output fall time (90% to 10%) 0.27 0.27 0.27 0.27 ns output noise (i outfs = 20ma) 1471 465 117 37 pa/hz spurious free dynamic range (sfdr) f dac = 125 msps, f out = 10 mhz 76 85 85 85 dbc f dac = 125 msps, f out = 50 mhz 55 55 55 55 dbc two tone intermodulation distortion (imd) f dac = 125 msps, f out = 10 mhz 81 81 81 82 dbc f dac = 125 msps, f out = 50 mhz 60 60 60 61 dbc noise spectral density ( nsd) , eight - tone, 500 khz tone spacing f dac = 125 msps, f out = 1 mhz ?131 ?141 ?153 ?163 dbc/hz f dac = 125 msps, f out = 10 mhz ?132 ?143 ?153 ?157 dbc/hz f dac = 125 msps, f out = 50 mhz ?128 ?138 ?146 ?149 dbc/hz w- cdma adjacent channel leakage ratio (aclr), single carrier f dac = 61.44 msps, f out = 20 mhz ?78 ?78 ?78 ? 78 dbc f dac = 122.88 msps, f out = 30 mhz ?80 ?80 ?80 ?80 dbc t min to t max , avdd = 1.8 v, dvdd = 1.8 v, dvddio = 1.8 v, cvdd = 1.8 v, i xoutfs = 8 ma, maximum sample rate, unless otherwise noted. table 4 . parameter ad9114 ad9115 ad9116 ad9117 unit min typ max min typ max min typ max min typ max spurious free dynamic range (sfdr) f dac = 125 msps, f out = 10 mhz 73 76 76 76 dbc f dac = 125 msps, f out = 50 m hz 48 48 48 48 dbc two tone intermodulation distortion (imd) f dac = 125 msps, f out = 10 mhz 76 76 76 76 dbc f dac = 125 msps, f out = 50 mhz 50 50 50 50 dbc noise spectral density (nsd) , eight - tone, 500 khz tone spaci ng f dac = 125 msps, f out = 1 mhz ? 131 ? 143 ? 152 ? 158 dbc/hz f dac = 125 msps, f out = 10 mhz ?132 ?143 ?151 ?152 dbc/hz f dac = 125 msps, f out = 50 mhz ?128 ?138 ?140 ?141 dbc/hz w- cdma adjacent channel leakage ratio ( aclr), single carrier f dac = 61.44 msps, f out = 20 mhz ?69 ?69 ?69 ?69 dbc f dac = 122.88 msps, f out = 30 mhz ? 72 ? 72 ? 72 ? 72 dbc
data sheet ad9114/ad9115/ad9116/ad9117 rev. d | page 9 of 52 absolute maximum rat ings table 5. parameter rating avdd, dvddio, cvd d to avss, dvss, cvss ?0.3 v to +3.9 v dvdd to dvss ?0.3 v to +2.1 v avss to dvss, cvss ?0.3 v to +0.3 v dvss to avss, cvss ?0.3 v to +0.3 v cvss to avss, dvss ? 0.3 v to +0.3 v refio , fsadjq, fsadji, cmlq, cmli to avss ? 0.3 v to avdd + 0.3 v qoutp, qoutn, ioutp, ioutn, rlqp, rlqn, rlip, rlin to avss ? 1.0 v to avdd + 0.3 v dbn 1 (msb) to d0 (lsb) , cs , sclk, sdio, reset to dvss ? 0.3 v to dvdd io + 0.3 v clkin to cvss ? 0.3 v to cvdd + 0.3 v junction temperature 125c storage tempe rature range ? 65c to +150c 1 n stands for 7 for the ad9114, 9 for the ad9115, 11 for the ad9116, and 13 for the ad9117 . stresses at or above those listed under absolute maximum ratings may cause permanent damage to the product. this is a stress rating o nly; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. operation beyond the maximum operating conditions for extended periods may affect product relia bility. thermal resistance table 6 . package type ja jb 1 jc 1 unit 40 - lead lfcsp ( w ith no airflow movement) 29.8 19.0 3.4 c/w 1 these calculations are intended to represent the thermal performance of the indicated packages using a jedec multilayer test board. do not assum e the same level of thermal p erformance in actual applications without a careful inspection of the conditions in the application to determine that they are similar to those assumed in these calculations. esd caution
ad9114/ad9115/ad9116/ad9117 data sheet rev. d | page 10 of 52 pin configurations and function descriptions pin 1 indic at or 1 db5 2 db4 3 db3 4 db2 5 dvddio 6 dvss 7 dvdd 8 db1 9 db0 (lsb) 10 nc 23 24 25 26 27 28 29 30 2221 11 nc 12 nc 13 nc 15 nc 17 cvdd 16 dclkio 18 clkin 19 cvss 20 cmlq 14 nc 33 fsadji/auxi 34 refio 35 reset/pinmd 36 sclk/clkmd 37 sdio/form at 38 cs/pwrdn 39 db7 (msb) 40 db6 32 fsadjq/auxq 31 cmli top view (not to scale) ad9114 07466-005 notes 1. nc = no connect 2. the exposed pad is connected to avss and must be soldered to the ground plane. exposed metal at package corners is connected to this pad. qout p rlq p avss a vdd rli p iout p ioutn rlin qoutn rlqn figure 2 . ad9114 pin configuration table 7 . ad9114 pin function descriptions pin no. mnemonic description 1 to 4 db[5:2] digital inputs. 5 dvddio digital i/o supply voltage input (1.8 v to 3.3 v nominal). 6 dvss digital common. 7 dvdd digital core supply voltage output (1.8 v). strap dvdd to dvddio at 1.8 v. if dvddio > 1.8 v, bypass dvdd with a 1.0 f capacitor; however, do not otherwise connect it. the ldo sho uld not drive external loads. 8 db1 digital in puts 9 db0 (lsb) digital input (lsb). 10 to 15 nc no connect. these pins are not connected to the chip. 16 dclkio data input/output clock. clock used to qualify input data. 17 cvdd sampling clock supply voltage input (1.8 v to 3.3 v). cvd d must be dvdd. 18 clkin lvcmos sampling clock input. 19 cvss sampling clock supply voltage common. 20 cmlq q dac output common - mode level. when the internal on - chip (qr cml ) is enabled, this pin is connected to the on - chip qr cml resistor. it is recommended to leave this pin unconnected. when the internal on - chip (qr cml ) is disabled, this pin is the common - mode load for q dac and must be connected to avss through a resistor, see the using the internal terminatio n resistors section. recommended value for this external resistor is 0 . 21 rlqn load resistor (62.5 ) to the cmlq pin. for the internal load resistor to be used, this pin should be tied to qoutn externally. 22 qoutn complementary q dac current output. full - scale current is sourced when all data bits are 0s. 23 qoutp q dac current output. full - scale current is sourced when all data bits are 1s. 24 rlqp load resistor (62.5 ) to the cmlq pin. for the internal load resistor to be used, this pin should be tied to qoutp externally. 25 avss analog common. 26 avdd analog su pply voltage input (1.8 v to 3.3 v). 27 rlip load resistor (62.5 ) to the cmli pin. for the internal load resistor to be u sed, this pin should be tied to ioutp externally. 28 ioutp i dac current output. full - scale current is sourced when all data bits a re 1s.
data sheet ad9114/ad9115/ad9116/ad9117 rev. d | page 11 of 52 pin no. mnemonic description 29 ioutn complementary i dac current output. full - scale current is sourced when all data bits are 0s. 30 rlin load resistor (62.5 ) to the cmli pin. for the internal load resistor to be u sed, this pin should be tied to ioutn externally. 31 cmli i dac output common - mode level. when the internal on - chip (ir cml ) is enabled, this pin is connected to the on - chip ir cml resistor. it is recommended to leave this pin unconnected. when the intern al on - chip (ir cml ) is disabled, this pin is the common - mode load for i dac and must be connected to avss through a resistor, see the using the internal termination resistors section. recommended value for this external resistor is 0 . 32 fsadjq/auxq full - scale current output adjust (fsadjq). when the internal on chip (qr set ) is disabled, this pin is the full - scale current output adjust for q dac and must be connected to avss through a resistor, see the theory of operation section. nominal value for this external resistor is 4 k for 8 ma out put current. auxiliary q dac output (auxq). when the internal on - chip (qr set ) is enabled, this pin is the auxiliary q dac output. 33 fsadji/auxi ful l- scale current output adjust (fsadji). when the internal on - chip (ir set ) is disabled, this pin is the full - scale current output adjust for i dac and must be connected to avss through a resistor, see the theory of o peration section. nominal value for this external resistor is 4 k for 8 ma output current. auxiliary i dac output (auxi). when the internal on - chip (ir set ) is enabled, it is the auxiliary i dac output. 34 refio reference input/output. serves as a reference input when the internal ref erence is disabled. provides a 1.0 v reference output when in internal reference mode (a 0.1 f capacitor to avss is required). 35 reset/pinmd this pin defines the operation mode of the part. a logic low (pull - down to dvss) sets the part in spi mode. pulse reset high to reset the spi registers to their default values. a logic high (pull - up to dvddio) puts the device into pin mode (pinmd). 36 sclk/clkmd clock input for serial port (sclk). in spi mode, this pin is the clock inp ut for the serial port. clock mode (clkmd). in pin mode, clkmd determines the phase of the internal retiming clock. when dclkio = clkin, tie it to 0. when dclkio clkin, pulse 0 to 1 to ed ge trigger the internal retime r , see the retimer section. 37 sdio/forma t serial port input/output (sdio). in spi mode, this pin is the bidirection al data line for the serial port. format pin (format). in pin mode, format determines the data format of digita l data. a logic low (pull - down to dvss) selects the binary input d ata format. a logic high (pull - up to dvddio) selects the twos complement input data format. 38 cs /pwrdn active low chip select ( cs ). in spi mode, this pin serves as the active low chip select. power - down (pwrdn). in pin mode, a logic high (pull - up to dvddio) powers down the device, except for the spi port. 39 db7 (msb) digital input (msb). 40 db6 digital input. ep (epad) the exposed pad is connected to avss and must be soldered to the ground plane. exposed meta l at the package corners is connected to this pad.
ad9114/ad9115/ad9116/ad9117 data sheet rev. d | page 12 of 52 pin 1 indicator 1 db7 2 db6 3 db5 4 db4 5 dvddio 6 dvss 7 dvdd 8 db3 9 db2 10 db1 23 qoutp 24 rlqp 25 avss 26 avdd 27 rlip 28 ioutp 29 ioutn 30 rlin 22 qoutn 21 rlqn 1 1 d b 0 ( l s b ) 1 2 n c 1 3 n c 1 5 n c 1 7 c v d d 1 6 d c l k i o 1 8 c l k i n 1 9 c v s s 2 0 c m l q 1 4 n c 3 3 f s a d j i /a u x i 3 4 r e f io 3 5 r e s e t / p i n m d 3 6 s c l k /c l k m d 3 7 s d i o /f o r m a t 3 8 c s /p w r d n 3 9 d b 9 ( m s b ) 4 0 d b 8 3 2 f s a d j q / a u x q 3 1 c m l i top view (not to scale) ad9115 07466-004 notes 1. nc = no connect 2 . the exposed pad is connected to avss and must be soldered to the ground plane. exposed metal at package corners is connected to this pad. figure 3. ad9115 pin configuration table 8. ad9115 pin function description pin no. mnemonic description 1 to 4 db[7:4] digital inputs. 5 dvddio digital i/o supply voltage input (1.8 v to 3.3 v nominal). 6 dvss digital common. 7 dvdd digital core supply voltage output (1.8 v). strap dvdd to dvddio at 1.8 v. if dvddio > 1.8 v, bypass dvdd with a 1.0 f capacitor; however, do not otherwise connect it. the ldo should not drive external loads. 8 to 10 db[3:1] digital inputs. 11 db0 (lsb) digital input (lsb). 12 to 15 nc no connect. these pins are not connected to the chip. 16 dclkio data input/output clock. clock used to qualify input data. 17 cvdd sampling clock supply voltage input (1.8 v to 3.3 v). cvdd must be dvdd. 18 clkin lvcmos sampling clock input. 19 cvss sampling clock supply voltage common. 20 cmlq q dac output common-mode level. when the internal on-chip (qr cml ) is enabled, this pin is connected to the on-chip qr cml resistor. it is recommended to leave this pin unconnected. when the internal on-chip (qr cml ) is disabled, this pin is the common-mode load for q dac and must be connected to avss through a resistor, see the using the internal termination resistors section. re commended value for this external resistor is 0 . 21 rlqn load resistor (62.5 ) to the cmlq pin. for the internal load resistor to be used, this pin should be tied to qoutn externally. 22 qoutn complementary q dac current output. full-scal e current is sourced when all data bits are 0s. 23 qoutp q dac current output. full-scale current is sourced when all data bits are 1s. 24 rlqp load resistor (62.5 ) to the cmlq pin. for the internal load resistor to be used, this pin should be tied to qoutp externally. 25 avss analog common. 26 avdd analog supply voltage input (1.8 v to 3.3 v). 27 rlip load resistor (62.5 ) to the cmli pin. for the internal load resistor to be used, this pin should be tied to ioutp externally. 28 ioutp i dac current output. full-scale curren t is sourced when all data bits are 1s. 29 ioutn complementary i dac current output. full-scal e current is sourced when all data bits are 0s. 30 rlin load resistor (62.5 ) to the cmli pin. for the internal load resistor to be used, this pin should be tied to ioutn externally.
data sheet ad9114/ad9115/ad9116/ad9117 rev. d | page 13 of 52 pin no. mnemonic description 31 cmli i dac output common - mode level. when the internal on - chip (ir cml ) is enabled, this pin is connected to the on - chip ir cml resistor. it is recommended to leave this pin unconnected. when the intern al on - chip (ir cml ) is disabled, this pin is the common - mode l oad for i dac and must be connected to avss through a resistor, see the using the internal termination resistors section. recommended value for this external resistor is 0 . 32 fsadjq/auxq full - scale current output adjust (fsadjq). when the internal on chip (qr set ) is disabled, this pin is the full - scale current output adjust for q dac and must be connected to avss through a resistor, see the theory of operation section. nominal value for this external resistor is 4 k for 8 ma output current . auxiliary q dac output (auxq). when the internal on - chip (qr set ) is enabled, this pin is the auxiliary q dac output. 33 fsadji/auxi ful l- scale current output adjust (fsadji). when the internal on - chip (ir set ) is disabled, this pin is the full - scale current output adjust for i dac and must be connected to avss through a resistor, see the theory of o peration section. nominal value for this external resistor is 4 k for 8 ma output current. auxiliary i dac output (auxi). when the internal on - chip (ir set ) is enabled, it is the auxiliary i dac output. 34 refio reference input/output. serves as a reference input when the internal ref erence is disabled. provides a 1.0 v reference output when in internal reference mode (a 0.1 f capacitor to avss is required). 35 reset/pinmd this pin defines the operation mode of the part. a logic low (pull - down to dvss) sets the part in spi mode. pulse reset high to reset the spi registers to their default values. a logic high (pull - up to dvddio) puts the device into pin mode (pinmd). 36 sclk/clkmd clock input for serial port (sclk). in spi mode, this pin is the clock inp ut for the serial port. clock mode (clkmd). in pin mode, clkmd determines the phase of the internal retiming clock. when dclkio = clkin, tie it to 0. when dclkio clkin, pulse 0 to 1 to ed ge trigger the internal retime, see the retimer section. 37 sdio/format serial port input/output (sdio). in spi mode, this pin is the bidirection al data line for the serial port. format pin (format). in pin mode, format determines the data format of digita l data. a logic low (pull - down to dvss) selects the binary input da ta format. a logic high (pull - up to dvddio) selects the twos complement input data format. 38 cs /pwrdn active low chip select ( cs ). in spi mode, this pin serves as the active low chip select. power - down (pwrdn). in pin mode, a logic high (pull - up to dvddio) powers down the device, except for the spi port. 39 db9 (msb) digital input (msb). 40 db82 digital input. ep (epad) the exposed pad is connected to avss and must be soldered to the ground plane. exposed meta l at the package corners is connected to this pad.
ad9114/ad9115/ad9116/ad9117 data sheet rev. d | page 14 of 52 pin 1 indic at or 1 db9 2 db8 3 db7 4 db6 5 dvddio 6 dvss 7 dvdd 8 db5 9 db4 10 db3 23 qout p 24 rlq p 25 avss 26 a vdd 27 rli p 28 iout p 29 ioutn 30 rlin 22 qoutn 21 rlqn 11 db2 12 db1 13 db0 (lsb) 15 nc 17 cvdd 16 dclkio 18 clkin 19 cvss 20 cmlq 14 nc 33 fsadji/auxi 34 refio 35 reset/pinmd 36 sclk/clkmd 37 sdio/form at 38 cs/pwrdn 39 db 1 1 (msb) 40 db10 32 fsadjq/auxq 31 cmli top view (not to scale) ad9116 notes 1. nc = no connect 2. the exposed pad is connected to avss and must be soldered to the ground plane. exposed metal at package corners is connected to this pad. 07466-003 figure 4 . ad9116 pin configuration table 9 . ad9116 pin function descriptions pin no. mnemonic description 1 to 4 db[9:6] digital inputs. 5 dvddio digital i/o supply voltage input (1.8 v to 3.3 v nominal). 6 dvss digital common. 7 dvdd digital core supply voltage output (1.8 v). strap dvdd to dvddio at 1.8 v. if dvddio > 1.8 v, bypass dvdd with a 1.0 f capacitor; however, do not otherwise connect it. the ldo should not drive external loads. 8 to 12 db[5:1] digital inputs. 13 db0 (lsb) digital input (lsb). 14, 15 nc no connect. these pins are not connected to the chip. 16 dclkio data input/output clock. clock used to qualify input data. 17 cvd d sampling clock supply voltage input (1.8 v to 3.3 v). cvdd must be dv dd. 18 clkin lvcmos sampling clock input. 19 cvss sampling clock supply voltage common. 20 cmlq q dac output common - mode level. when the internal on - chip (qr cml ) is enabled, this p in is connected to the on - chip qr cml resistor. it is recommended to leave this pin unconnected. when the internal on - chip (qr cml ) is disabled, this pin is the common - mode load for q dac and must be connected to avss through a resistor, see the using the internal termination resistors section. recommended value for this external resistor is 0 . 21 rlqn load resistor (62.5 ) to the cmlq pin. for the internal load resistor to be used, this pin should be tied to qoutn externally. 22 qoutn complementary q dac current output. full - scale current is sourced when all data bits are 0s. 23 qoutp q d ac current output. full - scale current is sourced when all data bits are 1s. 24 rlqp load resistor (62.5 ) to the cmlq pin. for the internal load resistor to be used, this pin should be tied to qoutp externally. 25 avss analog common. 26 avdd analog sup ply voltage input (1.8 v to 3.3 v). 27 rlip load resistor (62.5 ) to the cmli pin. for the internal load resistor to be u sed, this pin should be tied to ioutp externally. 28 ioutp i dac current output. full - scale current is sourced when all data bits ar e 1s. 29 ioutn complementary i dac current output. full - scale current is sourced when all data bits are 0s. 30 rlin load resistor (62.5 ) to the cmli pin. for the internal load resistor to be u sed, this pin should be tied to ioutn externally.
data sheet ad9114/ad9115/ad9116/ad9117 rev. d | page 15 of 52 pin no. mnemonic description 31 cmli i dac output common - mode level. when the internal on - chip (ir cml ) is enabled, this pin is connected to the on - chip ir cml resistor. it is recommended to leave this pin unconnected. when the intern al on - chip (ir cml ) is disabled, this pin is the common mode l oad for i dac and must be connected to avss through a resistor, see the using the internal termination resistors section. recommended value for this external resistor is 0 . 32 fsadjq/auxq full - scale current output adjust (fsadjq). when the internal on chip (qr set ) is disabled, this pin is the full - scale current output adjust for q dac and must be connected to avss through a resistor, see the theory of operation section. nominal value for this external resistor is 4 k for 8 ma output current . auxiliary q dac output (auxq). when the internal on - chip (qr set ) is enabled, this pin is the auxiliary q dac output. 33 fsadji/auxi ful l- scale current output adjust (fsadji). when the internal on - chip (ir set ) is disabled, this pin is the full - scale current output adjust for i dac and must be connected to avss through a resistor, see the theory of o peration section. nominal value for this external resistor is 4 k for 8 ma output current. auxiliary i dac output (auxi). when the internal on - chip (ir set ) is enabled, it is the auxiliary i dac output. 34 refio reference input/output. serves as a reference input when the internal ref erence is disabled. provides a 1.0 v reference output when in internal reference mode (a 0.1 f capacitor to avss is required). 35 reset/pinmd this pin defines the operation mode of the part. a logic low (pull - down to dvss) sets the part in spi mode. pulse reset high to reset the spi registers to their default values. a logic high (pull - up to dvddio) puts the device into pin mode (pinmd). 36 sclk/clkmd clock input for serial port (sclk). in spi mode, this pin is the clock inp ut for the serial port. clock mode (clkmd). in pin mode, clkmd determines the phase of the internal retiming clock. when dclkio = clkin, tie it to 0. when dclkio clkin, pulse 0 to 1 to ed ge trigger the internal retime, see the retimer section. 37 sdio/format serial port input/output (sdio). in spi mode, this pin is the bidirection al data line for the serial port. format pin (format). in pin mode, format determines the data format of digita l data. a logic low (pull - down to dvss) selects the binary input da ta format. a logic high (pull - up to dvddio) selects the twos complement input data format. 38 cs /pwrdn active low chip select ( cs ). in spi mode, this pin serves as the active low chip select. power - down (pwrdn). in pin mode, a logic high (pull - up to dvddio) powers down the device, except for the spi port. 39 db11 (msb) digital input (msb). 40 db10 digital input. ep (epad) the exposed pad is connected to avss and must be soldered to the ground plane. exposed me tal at the package corners is connected to this pad.
ad9114/ad9115/ad9116/ad9117 data sheet rev. d | page 16 of 52 pin 1 indicator 1 db11 2 db10 3 db9 4 db8 5 dvddio 6 dvss 7 dvdd 8 db7 9 db6 10 db5 23 qoutp 24 rlqp 25 avss 26 avdd 27 rlip 28 ioutp 29 ioutn 30 rlin 22 qoutn 21 rlqn 1 1 d b 4 1 2 d b 3 1 3 d b 2 1 5 d b 0 ( l s b ) 1 7 c v d d 1 6 d c l k io 1 8 c l k i n 1 9 c v s s 2 0 c m l q 1 4 d b 1 3 3 f s a d j i /a u x i 3 4 r e f io 3 5 r e s e t /p in m d 3 6 s c l k /c l k m d 3 7 s d i o /f o r m a t 3 8 c s /p w r d n 3 9 d b 1 3 ( m s b ) 4 0 d b 1 2 3 2 f s a d j q /a u x q 3 1 c m l i top view (not to scale) ad9117 07466-002 notes 1. the exposed pad is connected to avss and must be soldered to the ground plane. exposed metal at package corners is connected to this pad. figure 5. ad9117 pin configuration table 10. ad9117 pin function descriptions pin no. mnemonic description 1 to 4 db[11:8] digital inputs. 5 dvddio digital i/o supply voltage input (1.8 v to 3.3 v nominal). 6 dvss digital common. 7 dvdd digital core supply voltage output (1.8 v). strap dvdd to dvddio at 1.8 v. if dvddio > 1.8 v, bypass dvdd with a 1.0 f capacitor; however, do not otherwise connect it. the ldo should not drive external loads. 8 to 14 db[7:1] digital inputs. 15 db0 (lsb) digital input (lsb). 16 dclkio data input/output clock. clock used to qualify input data. 17 cvdd sampling clock supply voltage input (1.8 v to 3.3 v). cvdd must be dvdd. 18 clkin lvcmos sampling clock input. 19 cvss sampling clock supply voltage common. 20 cmlq q dac output common-mode level. when the internal on-chip (qr cml ) is enabled, this pin is connected to the on-chip qr cml resistor. it is recommended to leave this pin unconnected. when the internal on-chip (qr cml ) is disabled, this pin is the common-mode load for q dac and must be connected to avss through a resistor, see the using the internal termination resistors section. recommended value for this external resistor is 0 . 21 rlqn load resistor (62.5 ) to the cmlq pin. for the internal load resistor to be used, this pin should be tied to qoutn externally. 22 qoutn complementary q dac current output. full-scal e current is sourced when all data bits are 0s. 23 qoutp q dac current output. full-scale current is sourced when all data bits are 1s. 24 rlqp load resistor (62.5 ) to the cmlq pin. for the internal load resistor to be used, this pin should be tied to qoutp externally. 25 avss analog common. 26 avdd analog supply voltage input (1.8 v to 3.3 v). 27 rlip load resistor (62.5 ) to the cmli pin. for the internal load resistor to be used, this pin should be tied to ioutp externally. 28 ioutp i dac current output. full-scale curren t is sourced when all data bits are 1s. 29 ioutn complementary i dac current output. full-scal e current is sourced when all data bits are 0s. 30 rlin load resistor (62.5 ) to the cmli pin. for the internal load resistor to be used, this pin should be tied to ioutn externally.
data sheet ad9114/ad9115/ad9116/ad9117 rev. d | page 17 of 52 pin n o. mnemonic description 31 cmli i dac output common - mode level. when the internal on - chip ( ir cml ) is enabled, this pin is connected to the on -c hip ir cml resistor. it is recommended to leave this pin unconnected. when the internal on - chip ( ir cml ) is disabled, this pin is the c ommon -m ode l oad for i dac and must be connected to avss through a resistor , see the using the internal termination resistors section . recommended value for this external resistor is 0 . 32 fsadjq/auxq full - scale current output adjust (fsadjq). when the internal on chip (qr set ) is disabled, this pin is the full - scale current output adjust for q dac and must be connected to avss through a resistor, see the theory of operation section. nominal value for this external resistor is 4 k for 8 ma output current . auxiliary q dac output (auxq). when the internal on - chip (qr set ) is enabled, this pin is the auxiliary q dac output. 33 fsadji/auxi ful l- scale current output adjust (fsadji). when the internal on - chip (ir set ) is disabled, this pin is the full - scale current output adjust for i dac and must be connected to avss through a resistor, see the theory of o peration section. nominal value for this external resistor is 4 k for 8 ma output current. auxiliary i dac output (auxi). when the internal on - chip (ir set ) is enabled, it is the auxiliary i dac output. 34 refio reference input/output. serves as a reference input when the internal reference is disabled. provides a 1.0 v reference output when in internal reference mode ( a 0.1 f capacitor to avss is required). 35 reset/pinmd this pin defines the operation mode of the part. a logic low ( pull - down to dvss) sets the part in spi mode. pulse reset high to reset the s pi registers to their default values. a logic high (pull - up to dvddio) puts the device into pin mode (pinmd) . 36 sclk/clkmd clock input for serial port (sclk). in spi mode, this pin is the clock inp ut for the serial port. clock mode (clkmd). in pin mode, clkmd determines the phase of the internal retiming clock. when dclkio = clkin, tie it to 0. when dclkio clkin, pulse 0 to 1 to ed ge trigger the internal retime, see the retimer section. 37 sdio/format serial port input/output (sdio). in spi mode, this pin is the bidirection al data line for the serial port. format pin (format). in pin mode, format determines the data format of digita l data. a logic low (pull - down to dvss) selects the binary input da ta format. a logic high (pull - up to dvddio) selects the twos complement input data format. 38 cs /pwrdn active low chip select ( cs ). in spi mode, this pin serves as the active low chip select. power - down (pwrdn). in pin mode, a logic high (pull - up to dvddio) powers down the device, except for the spi port. 39 db13 (msb) digital input (msb). 40 db12 digital input. ep (epad) the exposed pad is connected to avss and must be soldered to the ground plane. exposed me tal at the package corners is connected to this pad.
ad9114/ad9115/ad9116/ad9117 data sheet rev. d | page 18 of 52 typical performance characteristics avdd, dvdd, dvddio, cvdd = 1.8 v, i xoutfs = 8 ma, maximum sample rate (125 msps), unless otherwise noted. 2.0 1.5 1.0 0.5 0 C0.5 C1.0 C2.0 C1.5 0 2048 4096 6144 8192 10,240 12,288 14,336 16,384 code precalibration inl (lsb) 07466-006 figure 6. ad9117 precalibration inl at 1.8 v, 8 ma (dvdd = 1.8 v) 2.0 1.5 1.0 0.5 0 C0.5 C1.0 C2.0 C1.5 0 2048 4096 6144 8192 10,240 12,288 14,336 16,384 code precalibration dnl (lsb) 07466-007 figure 7. ad9117 precalibration dnl at 1.8 v, 8 ma (dvdd = 1.8 v) 1.5 1.0 0.5 0 C0.5 C1.0 C1.5 0 2048 4096 6144 8192 10,240 12,288 14,336 16,384 code precalibration inl (lsb) 0 7466-008 figure 8. ad9117 precalibration inl at 3.3 v, 20 ma (dvdd = 1.8 v) 2.0 1.5 1.0 0.5 0 C0.5 C1.0 C2.0 C1.5 0 2048 4096 6144 8192 10,240 12,288 14,336 16,384 code postcalibration inl (lsb) 07466-009 figure 9. ad9117 postcalibration inl at 1.8 v, 8 ma (dvdd = 1.8 v) 2.0 1.5 1.0 0.5 0 C0.5 C1.0 C2.0 C1.5 0 2048 4096 6144 8192 10,240 12,288 14,336 16,384 code postcalibration dnl (lsb) 07466-010 figure 10. ad9117 postcalibration dnl at 1.8 v, 8 ma (dvdd = 1.8 v) 1.5 1.0 0.5 0 C0.5 C1.0 C1.5 0 2048 4096 6144 8192 10,240 12,288 14,336 16,384 code postcalibration inl (lsb) 0 7466-011 figure 11. ad9117 postcalibration inl at 3.3 v, 20 ma (dvdd = 1.8 v)
data sheet ad9114/ad9115/ad9116/ad9117 rev. d | page 19 of 52 1.5 1.0 0.5 0 C0.5 C1.0 C1.5 0 2048 4096 6144 8192 10,240 12,288 14,336 16,384 code precalibration dnl (lsb) 0 7466-012 figure 12. ad9117 precalibration dnl at 3.3 v, 20 ma 0.8 0.6 0.4 0.2 0 C0.2 C0.4 C0.6 C0.8 0 512 1024 1536 2048 2560 3072 3584 4096 code precalibration inl (lsb) 0 7466-013 figure 13. ad9116 precalibration inl at 1.8 v, 8 ma 0.6 0.4 0.2 0 C0.2 C0.4 C0.6 0 512 1024 1536 2048 2560 3072 3584 4096 code precalibration dnl (lsb) 0 7466-014 figure 14. ad9116 precalibration dnl at 1.8 v, 8 ma 1.5 1.0 0.5 0 C0.5 C1.0 C1.5 0 2048 4096 6144 8192 10,240 12,288 14,336 16,384 code postcalibration dnl (lsb) 0 7466-015 figure 15. ad9117 postcalibration dnl at 3.3 v, 20 ma 0.8 0.6 0.4 0.2 0 C0.2 C0.4 C0.6 C0.8 0 512 1024 1536 2048 2560 3072 3584 4096 code postcalibration inl (lsb) 0 7466-016 figure 16. ad9116 postcalibration inl at 1.8 v, 8 ma 0.6 0.4 0.2 0 C0.2 C0.4 C0.6 0 512 1024 1536 2048 2560 3072 3584 4096 code postcalibration dnl (lsb) 0 7466-017 figure 17. ad9116 postcalibration dnl at 1.8 v, 8 ma
ad9114/ad9115/ad9116/ad9117 data sheet rev. d | page 20 of 52 0.8 0.6 0.4 0.2 0 C0.2 C0.4 C0.6 C0.8 0 512 1024 1536 2048 2560 3072 3584 4096 code precalibration inl (lsb) 0 7466-018 figure 18. ad9116 precalibration inl at 3.3 v, 20 ma 0.5 0.4 0.3 0.2 0.1 0 C0.1 C0.2 C0.3 C0.5 C0.4 0 512 1024 1536 2048 2560 3072 3584 4096 code precalibration dnl (lsb) 0 7466-019 figure 19. ad9116 precalibration dnl at 3.3 v, 20 ma 0.25 0.20 0.15 0.10 0.05 0 C0.05 C0.10 C0.15 C0.25 C0.20 0 128 256 384 512 640 768 896 1024 code precalibration inl (lsb) 0 7466-020 figure 20. ad9115 precalibration inl at 1.8 v, 8 ma 0.8 0.6 0.4 0.2 0 C0.2 C0.4 C0.6 C0.8 0 512 1024 1536 2048 2560 3072 3584 4096 code postcalibration inl (lsb) 0 7466-021 figure 21. ad9116 postcalibration inl at 3.3 v, 20 ma 0.5 0.4 0.3 0.2 0.1 0 C0.1 C0.2 C0.3 C0.5 C0.4 0 512 1024 1536 2048 2560 3072 3584 4096 code postcalibration dnl (lsb) 07466-022 figure 22. ad9116 postcalibration dnl at 3.3 v, 20 ma 0.25 0.20 0.15 0.10 0.05 0 C0.05 C0.10 C0.15 C0.25 C0.20 0 128 256 384 512 640 768 896 1024 code postcalibration inl (lsb) 07466-023 figure 23. ad9115 postcalibration inl at 1.8 v, 8 ma
data sheet ad9114/ad9115/ad9116/ad9117 rev. d | page 21 of 52 0.08 0.06 0.02 0.04 C0.02 0 C0.04 C0.06 C0.08 0 128 256 384 512 640 768 896 1024 code precalibration dnl (lsb) 07466-024 figure 24. ad9115 precalibration dnl at 1.8 v, 8 ma 0.25 0.20 0.15 0.10 0.05 0 C0.05 C0.10 C0.15 C0.25 C0.20 0 128 256 384 512 640 768 896 1024 code precalibration inl (lsb) 0 7466-025 figure 25. ad9115 precalibration inl at 3.3 v, 20 ma 0.08 0.06 0.02 0.04 C0.02 0 C0.04 C0.06 C0.08 0 128 256 384 512 640 768 896 1024 code precalibration dnl (lsb) 07466-026 figure 26. ad9115 precalibration dnl at 3.3 v, 20 ma 0.08 0.06 0.02 0.04 C0.02 0 C0.04 C0.06 C0.08 0 128 256 384 512 640 768 896 1024 code postcalibration dnl (lsb) 07466-027 figure 27. ad9115 postcalibration dnl at 1.8 v, 8 ma 0.25 0.20 0.15 0.10 0.05 0 C0.05 C0.10 C0.15 C0.25 C0.20 0 128 256 384 512 640 768 896 1024 code postcalibration inl (lsb) 0 7466-028 figure 28. ad9115 postcalibration inl at 3.3 v, 20 ma 0.08 0.06 0.02 0.04 C0.02 0 C0.04 C0.06 C0.08 0 128 256 384 512 640 768 896 1024 code postcalibration dnl (lsb) 07466-029 figure 29. ad9115 postcalibration dnl at 3.3 v, 20 ma
ad9114/ad9115/ad9116/ad9117 data sheet rev. d | page 22 of 52 0.035 0.015 0.025 0.005 0 C0.005 C0.015 C0.025 C0.035 0 32 64 96 128 160 192 224 256 code precalibration inl (lsb) 07466-030 figure 30 . ad 9114 precalibration inl at 1.8 v , 8 ma 0.025 0.020 0.015 0.010 0.005 0 C0.005 C0.010 C0.015 C0.020 C0.025 0 32 64 96 128 160 192 224 256 code precalibration dnl (lsb) 07466-031 figure 31 . ad 9114 precalibration dnl at 1.8 v , 8 ma 0.03 0.02 0.01 0 C0.01 C0.02 C0.03 0 32 64 96 128 160 192 224 256 code precalibration inl (lsb) 07466-032 figure 32 . ad 9114 precalibration inl at 3.3 v , 20 ma 0.035 0.015 0.025 0.005 0 C0.005 C0.015 C0.025 C0.035 0 32 64 96 128 160 192 224 256 code postcalibration inl (lsb) 07466-033 figure 33 . ad 9114 postcalibration inl at 1.8 v , 8 ma 0.025 0.020 0.015 0.010 0.005 0 C0.005 C0.010 C0.015 C0.020 C0.025 0 32 64 96 128 160 192 224 256 code postcalibration dnl (lsb) 07466-034 figure 34 . ad 9114 postcalibration dnl at 1.8 v , 8 ma 0.03 0.02 0.01 0 C0.01 C0.02 C0.03 0 32 64 96 128 160 192 224 256 code postcalibration inl (lsb) 07466-035 figure 35 . ad 9114 postcalibration inl at 3.3 v , 20 ma
data sheet ad9114/ad9115/ad9116/ad9117 rev. d | page 23 of 52 0.025 0.020 0.015 0.010 0.005 0 C0.005 C0.010 C0.015 C0.020 C0.025 0 32 64 96 128 160 192 224 256 code precalibration dnl (lsb) 07466-036 figure 36. ad9114 precalibration dnl at 3.3 v, 20 ma C 124 C130C136 C142 C148 C154 C160 0 1 02 03 04 05 0 f out (mhz) nsd (dbc) ad9117 ad9116 ad9115 ad9114 07466-137 figure 37. nsd at 8 ma vs. f out , 1.8 v C160 C 136 C139 C142 C145 C148 C151 C154 C157 0 1 02 03 0 5 1 52 53 5 4 0 4 5 5 0 5 5 07466-201 f out (mhz) nsd (dbm/hz) C40c +85c +25c figure 38. ad9117 nsd at three temperatures 8 ma vs. f out , 1.8 v 0.025 0.020 0.015 0.010 0.005 0 C0.005 C0.010 C0.015 C0.020 C0.025 03 26 49 61 2 8 code 160 192 224 256 postcalibration dnl (lsb) 07466-039 figure 39. ad9114 postcalibration dnl at 3.3 v, 20 ma C166 C160 C154 C148 C142 C136 C130 C 124 0 1 02 03 0 5 1 52 53 5 4 0 4 5 5 0 5 5 07466-200 f out (mhz) nsd (dbc) ad9117 ad9116 ad9115 ad9114 figure 40. nsd at 20 ma vs. f out , 3.3 v C160 C 136 C139 C142 C145 C148 C151 C154 C157 0 1 02 03 0 5 1 52 53 5 4 0 4 5 5 0 5 5 07466-202 f out (mhz) nsd (dbm/hz) C40c +85c +25c figure 41. ad9117 nsd at three temperatures 8 ma vs. f out , 3.3 v
ad9114/ad9115/ad9116/ad9117 data sheet rev. d | page 24 of 52 C16 6 C16 0 C15 4 C14 8 C14 2 C13 6 C13 0 0 5 1 0 15 20 25 30 35 40 45 50 55 f out (mhz) nsd (dbc) 1.8v, 4ma 1.8v, 8ma 07466-142 figure 42 . ad9117 nsd at two output currents vs. f out , 1.8 v 07466-090 start 1mhz 1.5mhz/div stop 16mhz (dbm) 0 C10C20 C30 C40 C50 C60 C70 C80 C90 C100 figure 43 . ad9117 two tone spectrum at 1.8 v 50 60 70 80 90 5 10 15 20 25 30 35 40 45 50 f out (mhz) imd ( dbc ) ad9117 ad9116 ad9115 ad9114 07466-144 figure 44 . all imd 8 ma vs. f out , 1.8 v C16 6 C16 0 C15 4 C14 8 C14 2 C13 6 C13 0 0 5 10 15 20 25 30 35 40 45 50 55 f ou t (mhz) nsd (dbc) 3.3v, 20ma 3.3v, 8ma 3.3v, 4ma 07466-145 figure 45 . ad9117 nsd a t three output currents v s. f out , 3.3 v 07466-091 start 1mhz 1.5mhz/div stop 16mhz (dbm) 0 C10C20 C30 C40 C50 C60 C70 C80 C90 C100 figure 46 . ad9117 two tone spectrum at 3.3 v 54 66 60 72 84 78 96 90 5 10 15 20 25 30 35 40 45 50 ad9117 ad9116 ad9115 ad9114 f out (mhz) imd ( dbc ) 07466-147 figure 47 . all imd 20 ma vs. f out , 3.3 v
data sheet ad9114/ad9115/ad9116/ad9117 rev. d | page 25 of 52 48 8478 72 66 60 54 5 101520253035404550 07466-195 f out (mhz) imd (dbc) C40c +85c +25c figure 48. ad9117 imd at three temperatures 8 ma vs. f out , 1.8 v 45 50 55 60 65 70 75 80 85 90 5 101520253035404550 0db C3db C6db 07466-092 f out (mhz) imd (dbc) figure 49. ad9117 imd at three digital signal levels vs. f out , 1.8 v 50 56 62 68 74 80 86 5 101520253035404550 f out (mhz) imd (dbc) 4ma 8ma 07466-150 figure 50. ad9117 imd at two output currents vs. f out , 1.8 v 63 9087 84 81 78 75 72 69 66 5 101520253035404550 07466-196 f out (mhz) imd (dbc) C40c +85c +25c figure 51. ad9117 imd at three temperatures 20 ma vs. f out , 3.3 v 55 60 65 70 75 80 85 90 5 101520253035404550 0db C3db C6db 07466-093 f in (mhz) imd (dbc) figure 52. ad9117 imd at three digital signal levels vs. f out , 3.3 v 56 62 68 74 80 9286 5 101520253035404550 f out (mhz) imd (dbc) 4ma 20ma 8ma 07466-153 figure 53. ad9117 imd at three output currents vs. f out , 3.3 v
ad9114/ad9115/ad9116/ad9117 data sheet rev. d | page 26 of 52 07466-088 start 1mhz 1.5mhz/div stop 16mhz (dbm) 0 C10C20 C30 C40 C50 C60 C70 C80 C90 C100 figure 54. ad9117 singe tone spectrum, 1.8 v 40 50 60 70 80 90 0 1 02 03 04 05 06 0 f out (mhz) sfdr (dbc) ad9117 ad9116 ad9115 ad9114 07466-155 figure 55. sfdr at 8 ma vs. f out , 1.8 v 42 48 54 60 66 72 78 84 90 0 5 10 15 20 25 30 35 40 45 50 55 60 f out (mhz) sfdr (dbc) C40c +25c +85c 07466-156 figure 56. ad9117 sfdr at three temperatures 8 ma vs. f out , 1.8 v 07466-089 start 1mhz 1.5mhz/div stop 16mhz (dbm) 0 C10C20 C30 C40 C50 C60 C70 C80 C90 C100 figure 57. ad9117 singe tone spectrum, 3.3 v 54 60 66 72 8478 90 96 0 1 02 03 04 05 06 0 f out (mhz) sfdr (dbc) ad9117 ad9116 ad9115 ad9114 07466-158 figure 58. ad9117 sfdr at 20 ma vs. f out , 3.3 v 56 62 68 74 80 86 92 98 0 5 10 15 20 25 30 35 40 45 50 55 60 f out (mhz) sfdr (dbc) C40c +25c +85c 07466-159 figure 59. ad9117 sfdr at three temperatures 8 ma vs. f out , 3.3 v
data sheet ad9114/ad9115/ad9116/ad9117 rev. d | page 27 of 52 42 50 58 66 74 82 90 98 0 5 10 15 20 25 30 35 40 45 50 55 60 07466-094 f out (mhz) sfdr (dbc) 0db C6db C3db figure 60. ad9117 sfdr at three digital signal levels vs. f out , 1.8 v 42 48 54 60 66 72 78 84 90 96 0 1 02 03 04 05 06 0 f out (mhz) sfdr (dbc) 4ma 8ma 07466-161 figure 61. ad9117 sfdr at two currents vs. f out , 1.8 v center 22.90mhz total carrier power C12.17dbm/7.87420mhz ref carrier power C12.17dbm/4.03420mhz rcc filter: off filter alpha 0.22 1. C12.17dbm 5.000mhz 3.840mhz C77.40 C89.56 C78.68 C90.84 2. C80.85dbm 10.00mhz 3.840mhz C78.90 C91.06 C78.27 C90.43 15.00mhz 3.840mhz C78.02 C90.18 C70.99 C83.15 10db/di v vbw 300khz offset freq integ bw dbc dbm dbc lower upper dbm span 38.84mhz res bw 30khz sweep 126ms (601pts) step 2db ac coupled: unspecified below 20mhz input att 8.00db 07466-162 figure 62. ad9117 aclr one-carrier, 1.8 v 50 58 66 74 82 90 98 0 5 10 15 20 25 30 35 40 45 50 55 60 07466-095 f out (mhz) sfdr (dbc) 0db C6db C3db figure 63. ad9117 sfdr at three digital signal levels vs. f out ., 3.3 v 42 48 54 60 66 72 78 84 90 96 0 1 02 03 04 05 06 0 f out (mhz) sfdr (dbc) 4ma 8ma 20ma 07466-164 figure 64. ad9117 sfdr at three currents vs. f out , 3.3v center 22.90mhz 10db/di v vbw 300khz span 38.84mhz step 2db input att 8.00db total carrier power C12.17dbm/7.87420mhz ref carrier power C12.17dbm/4.03420mhz rcc filter: off filter alpha 0.22 1. C12.17dbm 5.000mhz 3.840mhz C77.40 C89.56 C78.68 C90.84 2. C80.85dbm 10.00mhz 3.840mhz C78.90 C91.06 C78.27 C90.43 15.00mhz 3.840mhz C78.02 C90.18 C70.99 C83.15 offset freq integ bw dbc dbm dbc lower upper res bw 30khz sweep 126ms (601pts) ac coupled: unspecified below 20mhz 07466-165 figure 65. ad9117 aclr one-carrier, 3.3 v
ad9114/ad9115/ad9116/ad9117 data sheet rev. d | page 28 of 52 C78 C72 C66 C 60 15 20 25 30 35 40 45 f out (mhz) aclr (dbc) 4ma precal 4ma postcal 8ma precal 8ma postcal 07466-166 figure 66. ad9117 one-carrier w-cdma first aclr vs. f out , 1.8 v C80 C74 C68 C 62 15 20 25 30 35 40 45 f out (mhz) aclr (dbc) 4ma precal 4ma postcal 8ma precal 8ma postcal 07466-167 figure 67. ad9117 one-carrier w-cdma second aclr vs. f out , 1.8 v C80 C74 C68 C 62 20 25 30 35 40 45 f out (mhz) aclr (dbc) 4ma precal 4ma postcal 8ma precal 8ma postcal 07466-168 figure 68. ad9117 one-carrier w-cdma third aclr vs. f out , 1.8 v C78 C72 C66 C 60 15 20 25 30 35 40 45 f out (mhz) aclr (dbc) 4ma precal 4ma postcal 8ma precal 8ma postcal 16ma precal 16ma postcal 07466-169 figure 69. ad9117 one-carrier w-cdma first aclr vs. f out , 3.3 v C80 C74 C68 C 62 15 25 35 45 f out (mhz) aclr (dbc) 4ma precal 4ma postcal 8ma precal 8ma postcal 16ma precal 16ma postcal 07466-170 figure 70. ad9117 one-carrier w-cdma second aclr vs. f out , 3.3 v C80 C74 C68 C 62 20 25 30 35 40 45 f out (mhz) aclr (dbc) 4ma precal 4ma postcal 8ma precal 8ma postcal 16ma precal 16ma postcal 07466-171 figure 71. ad9117 one-carrier w-cdma third aclr vs. f out , 3.3 v
data sheet ad9114/ad9115/ad9116/ad9117 rev. d | page 29 of 52 center 22.90mhz 10db/di v vbw 300khz span 38.84mhz step 2db input att 8.00db total carrier power C15.23dbm/7.87420mhz ref carrier power C18.09dbm/4.03420mhz rcc filter: off filter alpha 0.22 1. C18.09dbm 5.000mhz 3.840mhz C72.11 C90.24 C71.97 C90.09 2. C18.40dbm 10.00mhz 3.840mhz C72.98 C91.10 C72.55 C90.68 15.00mhz 3.840mhz C69.93 C88.05 C72.30 C90.42 offset freq integ bw dbc dbm dbc lower upper dbm res bw 30khz sweep 126ms (601pts) ac coupled: unspecified below 20mhz 07466-172 figure 72. ad9117 aclr two-carrier, 1.8 v C74 C68 C62 C56 C 50 15 20 25 30 35 40 f out (mhz) aclr (dbc) 4ma precal 4ma postcal 8ma precal 8ma postcal 07466-173 figure 73. ad9117 two-carrier w-cdma first aclr vs. f out , 1.8 v C74 C68 C62 C56 C 50 15 20 25 30 35 40 f out (mhz) aclr (dbc) 4ma precal 4ma postcal 8ma precal 8ma postcal 07466-174 figure 74. ad9117 two-carrier w-cdma second aclr vs. f out , 1.8 v center 22.90mhz 10db/di v vbw 300khz span 38.84mhz step 2db input att 8.00db total carrier power C15.23dbm/7.87420mhz ref carrier power C18.09dbm/4.03420mhz rcc filter: off filter alpha 0.22 1. C18.09dbm 5.000mhz 3.840mhz C72.11 C90.24 C71.97 C90.09 2. C18.40dbm 10.00mhz 3.840mhz C72.98 C91.10 C72.55 C90.68 15.00mhz 3.840mhz C69.93 C88.05 C72.30 C90.42 offset freq integ bw dbc dbm dbc lower upper dbm res bw 30khz sweep 126ms (601pts) ac coupled: unspecified below 20mhz 07466-175 figure 75. ad9117 aclr two-carrier, 3.3 v C74 C68 C62 C56 C 50 15 20 25 30 35 40 f out (mhz) aclr (dbc) 4ma precal 4ma postcal 8ma precal 8ma postcal 16ma precal 16ma postcal 07466-176 figure 76. ad9117 two-carrier w-cdma first aclr vs. f out , 3.3 v C74 C68 C62 C56 C 50 15 20 25 30 35 40 f out (mhz) aclr (dbc) 4ma precal 4ma postcal 8ma precal 8ma postcal 16ma precal 16ma postcal 07466-177 figure 77. ad9117 two-carrier w-cdma second aclr vs. f out , 3.3 v
ad9114/ad9115/ad9116/ad9117 data sheet rev. d | page 30 of 52 C74 C68 C56 C62 C 50 20 25 30 35 40 f out (mhz) aclr (dbc) 4ma precal 4ma postcal 8ma precal 8ma postcal 0 7466-178 figure 78. ad9117 two-carrier w-cdma third aclr vs. f out , 1.8 v 0.4 0.3 0.2 0.1 0 C0.1 C0.2 C0.3 C0.5 C0.4 0 code auxdac dnl (lsb) 128 256 384 512 640 768 896 1024 0 7466-047 figure 79. ad9114/ad9115/ad9116/ad9117 auxdac dnl cvdd dvdd avdd @ 4ma out avdd @ 8ma out total current @ 4ma out total current @ 8ma out 4030 20 10 0 0 20 40 60 80 100 120 140 f dac (mhz) supply current (ma) 07466-048 figure 80. ad9114/ad9115/ad9116/ad9117 supply current vs. f dac , 1.8 v C74 C68 C56 C62 C 50 20 25 30 35 40 f out (mhz) aclr (dbc) 4ma precal 4ma postcal 8ma precal 8ma postcal 16ma precal 16ma postcal 0 7466-181 figure 81. ad9117 two-carrier w-cdma third aclr vs. f out , 3.3 v 1.0 0.8 0.6 0.4 0.2 0 C0.2 C0.4 C0.6 C1.0 C0.8 0 code auxdac inl (lsb) 128 256 384 512 640 768 896 1024 0 7466-044 figure 82. ad9114/ad9115/ad9116/ad9117 auxdac inl 0 10 20 30 40 50 60 70 80 0 2 04 06 08 01 0 01 2 01 4 0 f dac (mhz) cur r ent ( m a) cvdd dvdd avdd @ 20ma out total current @ 20ma out total current @ 8ma out total current @ 4ma out avdd @ 8ma out avdd @ 4ma out 0 7466-183 figure 83. ad9114/ad9115/ad9116/ad9117supply current vs. f dac , 3.3 v
data sheet ad9114/ad9115/ad9116/ad9117 rev. d | page 31 of 52 terminology linearity error or integral nonlinearity (inl) linearity error is defined as the maximum deviation of the actual analog output from the ideal output, determined by a straight line drawn from zero scale to full scale. differential nonlinearity (dnl) dnl is the measure of the variation in analog value, normalized to full scale, associate d with a 1 lsb change in digital input code. monotonicity a dac is monotonic if the output either increases or rem ains constant as the digital input increases. offset error offset error is t he deviation of the output current from the ideal of zero. for i outp , the 0 ma output is expected when the inputs are all 0. for i outn , the 0 ma output is expect ed when all inputs are set to 1 . gain error gain error is t he difference between the actual and the ideal output span. the actual span is determined by the difference between the outp ut when all inputs are set to 1 and the output when all inputs are set to 0. output compliance range the o utput complian ce range is t he range of allowable voltage at the output of a current output dac. operation beyond the maximum compliance limits can cause either output stage saturation or breakdown, resulting in nonlinear performance. tempera ture drift temperature drift is specified as the maximum change from the ambient value (25c) to the value at either t min or t max . for offset and gain drift, the drift is repor ted in ppm of full - scale range per degree celsius (ppm fsr/c) . for reference drift, the drift is reported in p arts p er m illion per degree celsius (ppm/c). power supply rejection power supply rejection is t he maximum change in the full - scale output as the supplies are varied from minimum to maximum specified voltages. settling ti me settling time is t he time required for the output to reach and remain within a specified error band around its final value, measured from the start of the output transition. spurious free dynamic range (sfdr) sfdr is t he difference, in decibels (db) , be tween the peak amplitude of the output signal and the peak spurious signal between dc and the frequency equal to half the input data rate. total harmonic distortion (thd) thd is the ratio of the rms sum of the first six harmonic components to the rms value of the measured fundamental. it is expressed as a percentage (%) or in decibels (db) . signal - to - noise ratio (snr) snr is the ratio of the rms value of the measured output signal to the rms sum of all other spectral components below the nyquist frequency, excluding the first six harmonics and dc. the value for snr is expressed in decibels (db) . adjacent channel leakage ratio (aclr) aclr is t he ratio in decibels relative to the carrier ( dbc ) between the measured power within a channel relative to its adjac ent channel. complex image rejection in a traditional two - part upconversion, two images are created around the second if frequency. these images have the effect of wasting transmitter power and system bandwidth. by placing the real part of a second comple x modulator in series with the first complex modulator, either the upper or lower frequency image near the second if can be rejected.
ad9114/ad9115/ad9116/ad9117 data sheet rev. d | page 32 of 52 theory of operation i dac q dac aux1dac aux2dac band gap clock dist 10k ? qr set 2k ? ir set 2k ? i ref 100a ir cm 60 ? to 260 ? qr cm 60 ? to 260 ? 62.5 ? 62.5 ? 62.5 ? 62.5 ? spi interface 1 into 2 interleaved data interface i data q data 1.8v ldo 1v ad9117 rlin ioutn ioutp rlip avdd avss rlqp qoutp qoutn rlqn db11 db10 db9db8 dvddio dvss dvdd db7db6 db5 db12 db13 (msb) cs/pwrdn sdio/format sclk/clkmd reset/pinmd refio fsadjq/auxq fsadji/auxi cmli db4 db3 db2 db1 (lsb) db0 dclkio cvdd clkin cvss cmlq 07466-050 figure 84. simplified block diagram figure 84 shows a simplified block diagram of the ad9114/ ad9115/ad9116/ad9117 that consists of two dacs, digital control logic, and a full-scale output current control. each dac contains a pmos current source array capable of providing a maximum of 20 ma. the arrays are divided into 31 equal currents that make up the five most significant bits (msbs). the next four bits, or middle bits, consist of 15 equal current sources whose value is 1/16 of an msb current source. the remaining lsbs are binary weighted fractions of the current sources of the mid dle bits. implementing the middle and lower bits with current sources, instead of an r-2r ladder, enhances its dynamic performance for multitone or low amplitude signals and helps maintain the high output impedance of the main dacs (that is, >200 m). the current sources are switched to one or the other of the two output nodes (i outp or i outn ) via pmos differential current switches. the switches are based on the architecture that was pioneered in the ad976x family, with further refinements to reduce distortion contributed by the switching transient. this switch architecture also reduces various timing errors and provides matching complementary drive signals to the inputs of the differential current switches. the analog and digital i/o sections of the ad9114/ad9115/ ad9116/ad9117 have separate power supply inputs (avdd and dvddio) that can operate independently over a 1.8 v to 3.3 v range. the core digital section requires 1.8 v. an optional on-ch ip ldo is provided for dvddio supplies greater than 1.8 v, or the 1.8 v can be supplied directly through dvdd. a 1.0 f bypass capacitor at dvdd (pin 7) is required when using the ldo. the core is capable of operating at a rate of up to 125 msps. it consists of edge-triggered latches and the segment decoding logic circuitry. the analog section includes pmos current sources, associated differential switches, a 1.0 v band gap voltage reference, and a reference control amplifier. each dac full-scale output current is regulated by the reference control amplifier and can be set from 4 ma to 20 ma via an external resistor, xr set , connected to its full-scale adjust pin (fsadjx). the external resistor, in combination with both the reference control amplifier and voltage reference, v refio , sets the reference current, i xref , which is replicated to the segmented current sources with the proper scaling factor. the full-scale current, i xoutfs , is 32 i xref . optional on-chip xr set resistors are provided that can be pro- grammed between a nominal value of 1.6 k to 8 k (20 ma to 4 ma i xoutfs , respectively). the ad9114/ad9115/ad9116/ad9117 provide the option of setting the output common mode to a value other than agnd via the output common-mode pin (cmli and cmlq). this facilitates directly interfacing the output of the ad9114/ad9115/ad9116/ ad9117 to components that require common-mode levels greater than 0 v.
data sheet ad9114/ad9115/ad9116/ad9117 rev. d | page 33 of 52 serial peripheral in terface (spi) the serial port of the ad 9114/ad9115/ad9116/ad9117 is a flexible, synchronous serial commun ications port that allow s easy interfac ing to many industry - standard microcontrollers and micro - processors. the serial i/o is compatible with most synchronous transfer formats, including both the motorola spi and intel? ssr protocols. the interface allows read/write access to all registers that configure the ad 9114/ad9115/ad9116/ad9117 . single or multiple byte transfers are supported, as well as msb first or lsb first transfer formats. the serial interface port of th e ad 9114 / ad 9115 /ad 9116 /ad 9117 is configu red as a single i/o pin on the sdio pin. general operation of the serial interface there are two phases to a communication cycle on the ad 9114/ ad9115/ad9116/ad9117 . phase 1 is the instruction cycle, which is the writing of an instruc tion byte into the ad 9114/ad9115/ ad9116/ad9117 , coincid ing with the first eight sclk rising edges. in phase 2, t he instruction byte provides the serial port controller of the ad 9114/ad9115/ad9116/ad9117 with infor - mation regarding the data transfer cycle . the phase 1 instruct ion byte defines whether the upcoming data transfer is a read or write, the number of bytes in the data transfer, and the starting r egister add ress for the first byte of the data transfer. the first eig ht sclk rising edges of each communi cation cycle are u sed to write the instruction byte into the ad 9114/ad9115/ad9116/ad9117 . a logic 1 on pin 35 (reset/pinmd) , fo llowed by a l ogic 0, resets the spi port timing to the initial state of the instruction cycle. this is true regardless of the present state of the internal registers or the other signal levels present at the inputs to the spi port. if the spi port is in the midst of an instruction cycle or a data transfer cycle, none of the present data is written. the remaining sclk edges are for phase 2 of the com munication cycle. phase 2 is the actual data transfer between the ad 9114 / ad 9115 /ad 9116 /ad 9117 and the system controller. phase 2 of the communication cycle is a transfer of one, two, three, or four data bytes, as determined by the instruction byte. using a multibyte transfer is the preferred method. single byte data transfers are useful to reduce cpu overhead when register access requires one byte only. registers change immediately upon writing to the last bit of each transfer byte. instruction byte th e instruction byte contains the information shown in table 11 . table 11 . msb lsb db 7 db 6 db 5 db 4 db 3 db 2 db 1 db 0 r/ w n1 n0 a4 a3 a2 a1 a0 r/ w ( bit 7 of the instruction byte ) determines whether a read or a write data transfer occurs after the instruction byte wr ite. logic 1 indi cates a read operation. logic 0 indicates a write opera tion. n1 and n0 ( bit 6 and bit 5 of the instruction byte ) determi ne the number of bytes to be transferred during the data transfer cycle. the bit decodes are shown in table 12 . table 12 . byte transfer count n1 n0 description 0 0 transfer 1 byte 0 1 tr ansfer 2 bytes 1 0 transfer 3 bytes 1 1 transfer 4 bytes a4, a3, a2, a1, and a0 ( bit 4, bit 3, bit 2, bit 1, and bit 0 of the instruction byte) determine which register is accessed during the data transfer portion of the communications cycle. for multi - byte transfers, this address is the starting byte address. the following register addresses are generated internally by the ad 9114 /ad 9115 /ad 9116 /ad 9117 based on the lsbfirst bit (register 0x00, bit 6). serial interface por t pin descriptions sclk ? serial clo ck the serial clock pin is used to synchronize data to and from the ad9114/ad9115/ad9116/ad9117 and to run the internal state machines. the sclk maximum frequency is 25 mhz. all data input to the ad9114/ad9115/ad9116/ad9117 is registered on the rising edge of sclk. this is shown in figure 85 and figure 87 for write instructions where the sclk rising edges are line d up in the middle of the data. all da ta is driven out of the ad9114/ad9115/ ad9116/ad9117 on the falling edge of sclk. this is shown in figure 86 and figure 88 for read cycles where the sclk falling edges line up in the middle of the data in the data transfer cycle. cs ? chip select a n a ctive low input starts and gates a communication s cycle. it allows more than one device to be used on the same serial commu - nications lines. the sdio/format pin reaches a high imped ance state when this input is high. chip select should stay low during the entire communication cycle. sdio ? serial data i/o the sdio pin is used as a bidirectional data line to transmit and receive data.
ad9114/ad9115/ad9116/ad9117 data sheet rev. d | page 34 of 52 msb/lsb transfers the serial port of the ad9114/ad9115 /ad9116/ad9117 can support both most significant bit (msb) first or least significant bit (lsb) first data formats. this functionality is controlled by the lsbfirst bit (register 0x00, bit 6). the default is msb first (lsbfirst = 0). when lsbfirst = 0 (ms b first), the instruction and data bytes must be written from the most significant bit to the least significant bit. multibyte data transfers in msb first format start with an instruction byte that includes the register address of the most significant data byte. subsequent data bytes should follow in order from a high address to a low address. in msb first mode, the serial port internal byte address generator decrements for each data byte of the multibyte communication s cycle. when lsbfirst = 1 (lsb first), the instruction and data bytes must be written from the least significant bit to the most significant bit. multibyte data transfers in lsb first format start with an instruction byte that includes the register address of the least significant data byte fo llowed by multiple data bytes. the serial port internal byte address generator increments for each byte of the multibyte communication cycle. if the msb first mode is active, t he serial port controller data address of the ad 9114 /ad 9115 / ad 9116 /ad 9117 decrem ents from the data address written toward 0x00 for multibyte i/o operations. if the lsb first mode is active, t he serial port controller address increments from the data address written toward 0x1f for multibyte i/o operations. serial port operatio n the se rial port configuration of the ad 9114 /ad 9115 /ad 9116 / ad 9117 is controlled by register 0x00 . it is important to note that the configuration changes immediately upon writing to the last bit of the register. for multibyte transfers, writing to this register c an occur during the middle of the communication s cycle. care must be taken to compensate for this new configu - ration for the remaining bytes of the current communication s cycle. the same considerations apply to setting the software reset bit (register 0x00 , bit 5). all registers are set to their default values except register 0x00, which remains unchanged. use of single - byte transfers or init iating a software reset is recommended when changing serial port configurations to prevent unexpected device behavior . r/w n1 n0 a4 a3 a2 a1 a0 d7 n d6 n d5 n d0 0 d1 0 d2 0 d3 0 instruction cycle d at a transfer cycle cs sclk sdio 07466-291 figure 85 . serial register interface timing, msb first write r/w n1 n0 a4 a3 a2 a1 a0 d7 n d6 n d5 n d0 0 d1 0 d2 0 d3 0 instruction cycle d at a transfer cycle cs sclk sdio 07466-386 figure 86 . serial register interface timing, msb first read a0 a1 a2 a3 a4 n0 n1 r/w d0 0 d1 0 d2 0 d7 n d6 n d5 n d4 n instruction cycle d at a transfer cycle sclk sdio 07466-289 cs figure 87 . serial register interface timing, lsb fir st write a0 a1 a2 a3 a4 n0 n1 r/w d0 0 d1 0 d2 0 d7 n d6 n d5 n d4 n instruction cycle d at a transfer cycle sclk sdio cs 07466-388 figure 88 . serial register interface timing, l sb first read pin m ode the ad 9114/ad9115/ad9116/ad9117 can also be operated without ever writing to the serial port. with reset/pinmd (pin 35) t ied high, the sclk pin become s clkmd to provide for clock mode control ( s ee the retimer section) , the sdio pin becomes format and select s the input data format , and the cs /pw rdn pin serves to power down the device. the pins a re not latched at power up. if you change the format, it should change with about a 1s delay. operation is otherwise exactly as defined by the default register values in table 13 ; therefore, external resistors at fsadji and fsadjq are needed to set the dac currents , and both dacs are active. this is also a co nvenient quick checkout mode. dac currents can be externally adjusted in pin mode by sourci ng or sinking currents at the fsadji/auxi and fs adjq/auxq pins , as desired , with the fixed resistors installed. an o p amp output with appropriate series resistance is one of many possibilities. this has the same effect as changing the resistor value. place at least 10 k? resistor s in series right at the dac to guard again st accidental short c ircuits and noise modulation. the refio pin can be adjusted 25% in a similar manner , if desired.
data sheet ad9114/ad9115/ad9116/ad9117 rev. d | page 35 of 52 spi register map table 13 . name addr default bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 spi control 0x0 0 0x00 reserved lsbfirst reset lngins reserved power - down 0x01 0x40 ldooff ldostat pwrdn q dacoff i dacoff qclkoff iclkoff extref data control 0x02 0x34 twos reserved ifirst irising simulbit dci_en dcosgl dcodbl i dac gain 0x03 0x00 reserved i dacgain[5 :0] irset 0x04 0x00 irseten reserved irset[5:0] ircml 0x05 0x00 ircmlen reserved ircml[5:0] q dac gain 0x06 0x00 reserved q dacgain[5:0] qrset 0x07 0x00 qrseten reserved qrset[5:0] qrcml 0x08 0x00 qrcmlen reserved qrcml[5:0] auxdac q 0x09 0x00 qauxda c[7:0] aux ctlq 0x0a 0x00 qauxen qauxrng[1:0] qauxofs[2:0] qauxdac[9:8] auxdac i 0x0b 0x00 iauxdac[7:0] aux ctli 0x0c 0x00 iauxen iauxrng[1:0] iauxofs[2:0] iauxdac[9:8] reference resistor 0x0d 0x00 reserved rref[5:0] cal control 0x0e 0x00 preldq preld i calselq calseli calclk divsel[2:0] cal memory 0x0f 0x00 calstatq calstati reserved calmemq[1:0] calmemi[1:0] memory address 0x10 0x00 reserved memaddr[5:0] memory data 0x11 0x34 reserved memdata[5:0] memory r/w 0x12 0x00 calrstq calrsti calen smemwr smemrd uncalq uncali clkmode 0x14 0x00 clkmodeq[1:0] searching reacquire clkmoden clkmodei[1:0] version 0x1f 0x0 a version [7:0]
ad9114/ad9115/ad9116/ad9117 data sheet rev. d | page 36 of 52 spi register descrip tions reading these registers return s previously written values for all defined register bits, unless otherwise noted. table 14 . register address bit name description spi control 0x00 6 lsbfirst 0 (default): msb first per spi standard . 1: lsb first per spi standard . note that the user must always change the lsb/msb orde r in single - byte instructions to avoid erratic behavior due to bit order errors . 5 reset execute s software reset of spi and controllers, reload s default regist er values , except register 0x00 . 1: s et software reset; write 0 on the next (or any following) cycle to release reset . 4 lngins 0 (default): t he spi instruction word u s es a 5 - bit address . 1: t he spi instruction word u s es a 13 - bit address . power down 0x01 7 ldooff 0 (default): ldo voltage regulator on . 1: turns core ldo voltage regulator off. 6 ldostat 0: i ndicates that the core ldo voltage regulator is off. 1 (default): i ndicates that the core ldo voltage regulator is on. 5 pwrdn 0 (default): all analog, digital circuitry and spi logic are powered on . 1: p owers d own all analog and digital circuitry, except for spi logic. 4 q dacoff 0 (default): turns on q dac output current . 1: t urns off q dac output current. 3 i dacoff 0 (default): turns on i dac output current . 1: t urns off i dac output current. 2 qclkoff 0 (default): turns on q dac clock . 1: t urns off q dac clock. 1 iclkoff 0 (default): turns on i dac clock . 1: t urns off i dac clock. 0 extref 0 (default): turns on internal voltage reference . 1: p owers down the internal voltage reference (external reference required). data control 0x02 7 twos 0 (default): unsigned binary input data format . 1: t wos complement input data format . 5 ifirst 0: p airing of data ? q first of pair on data input pads . 1 (default): p airing o f data ? i first of pair on data input pads (default) . 4 irising 0: q data latched on dclkio rising edge . 1 (default): i data latched on dclkio rising edge (default) . 3 simulbit 0 (default): a llows simultaneous input and output enable on dclkio . 1: d isallows simultaneous input and output enable on dclkio . 2 dci_en controls the use of the dclkio pad for the data clock input . 0: d ata clock input disabled . 1 (default): d ata clock input enabled . 1 dcosgl controls the use of the dclk io pad for the data clock output . 0 (default): d ata clock output disabled . 1: d ata clock output enabled; regular strength driver . 0 dcodbl controls the use of the dclkio pad for the data clock output . 0 (default): dco d bl data clock output disabled . 1: dco d bl data clock output enabled; paralleled with dcosgl for 2 driv e current . i dac gain 0x03 5:0 i dacgain[5:0] dac i fine gain adjustment; alters the full - scale current , as shown in figure 99 . default idacgain = 0x00 .
data sheet ad9114/ad9115/ad9116/ad9117 rev. d | page 37 of 52 register address bit name description irset 0x04 7 irseten 0 (default): ir set resistor value for i channel is set by an external resistor connected to the fadji /auxi pin. nominal value for this external resistor is 4 k . 1: enables the on - chip ir set value to be changed for i channel. 5:0 irset[5:0] changes the value of the on - chip ir set resistor; this scales the full - scale current of the dac in ~0.25 db steps twos complement (nonlinear) , see figure 98 . 000000 (default): ir set = 2 k . 011111: ir set = 8 k . 100000: ir set = 1.6 k . 111111: ir set = 2 k . ircml 0x05 7 ircmlen 0 (default): ir cml resistor value for the i c hannel is set by an external r esistor connected to cmli pin. recommended value for this external resistor is 0 . 1: enables on - chip ir cml adjustment for i channel. 5:0 ircml[5:0] changes the value of the on - chip ir cml resistor for i c hannel; this adjusts the common - mode leve l of the dac output stage . 000000 (default): ir cml = 60 . 100000: ir cml = 160 . 111111: ir cml = 260 . q dac gain 0x06 5:0 q dacgain[5:0] dac q fine gain adjustment; alters the full - scale current , as shown in figure 99 . default qdacgain = 0x00 . qrset 0x07 7 qrseten 0 (default): qr set resistor value for q channel is set by an external resistor connected to fadji/auxi pin. nominal value for this external resistor is 4 k. 1: enables on - chip q r set adjustment for q channel. 5:0 qrset[5:0] changes the value of the on - chip qr set resistor; this scales the full - scale current of the dac in ~0.25 db steps twos comple ment (nonlinear) . 000000 (default): qr set = 2 k. 011111: qr set = 8 k. 100000: qr set = 1.6 k. 111111: qr set = 2 k. qrcml 0x08 7 qrcmlen 0 (default): qr cml resistor value for the q c hannel is set by an external resistor connected to cmlq pin. recommended value for this external resistor is 0 . 1: e nables on - chip qr cml adjustment. 5:0 qrcml[5:0] changes the value of the on - chip qr cml resistor for q c hannel; this adjusts the common - mode level of the dac output stage . 000000 (default): qr cml = 60 . 100000: qr cml = 160 . 111111: qr cml = 260 . auxdac q 0x09 7:0 qauxdac[7:0] auxdac q output voltage adjustment word lsbs . 0x3ff: s ets auxdac q output to full scale. 0x200: s ets auxdac q output to midscale. 0x000 (default): s ets auxdac q output to bottom of scale. aux ctlq 0x0a 7 qa uxen 0 (default): auxdac q output disabled . 1: enables auxdac q output. 6:5 qauxrng[1:0] 00 (default): s ets auxdac q output voltage range to 2 v . 01: se ts auxdac q output voltage range to 1.5 v. 10: s ets auxdac q output voltage range to 1.0 v. 11: s ets auxdac q output voltage range to 0.5 v. 4:2 qauxofs[2:0] 000 (default): s ets auxdac q top of range to 1.0 v . 001: s ets auxdac q top of range to 1.5 v. 010: s ets auxdac q top of range to 2.0 v. 011: s ets auxdac q top o f range to 2.5 v. 100: s ets auxdac q top of range to 2.9 v. 1:0 qauxdac[9:8] auxdac q output voltage adjustment word msbs (d efault = 00 ).
ad9114/ad9115/ad9116/ad9117 data sheet rev. d | page 38 of 52 register address bit name description auxdac i 0x0b 7:0 iauxdac[7:0] auxdac i output voltage adjustment word lsbs . 0x3ff: s ets auxdac i outpu t to full scale. 0x200: s ets auxdac i output to midscale. 0x000 (default): s ets auxdac i output to bottom of scale. aux ctli 0x0c 7 iauxen 0 (default): auxdac i output disabled . 1: enables auxdac i output. 6:5 iauxrng[1:0] 00 (default): s ets auxdac i output voltage range to 2 v . 01: s ets auxdac i output voltage range to 1.5 v. 10: s ets auxdac i output voltage range to 1.0 v. 11: s ets auxdac i output voltage range to 0.5 v. 4:2 iauxofs[2:0] 000 (default): s ets auxdac i t op of range to 1.0 v . 001: s ets auxdac i top of range to 1.5 v. 010: s ets auxdac i top of range to 2.0 v. 011: s ets auxdac i top of range to 2.5 v. 100: s ets auxdac i top of range to 2.9 v. 1:0 iauxdac[9:8] aux dac i output voltage a djustment word msbs (d efault = 00 ). reference resistor 0x0d 5:0 rref[5:0] permits an adjustment of the on - chip reference voltage and output at refio (see figure 97 ) twos complement . 000000 (default): s ets t he value of r ref to 10 k, v ref = 1.0 v. 011111: s ets the value of r ref to 12 k, v ref = 1.2 v. 100000: s ets the value of r ref to 8 k, v ref = 0.8 v. 111111: s ets the value of r ref to 10 k, v ref = 1.0 v. cal control 0x0e 7 preldq 0 (default): p reload s q dac calibration reference set to 32 . 1: p reload s q dac calibration reference set by user (cal address 1). 6 preldi 0 (default): p reload s i dac calibration reference set to 32 . 1: p reload s i dac calibration reference set by user (cal address 1). 5 calselq 0 (default): q dac self - calibration done . 1: s elects q dac self - calibration. 4 calseli 0 (default): i dac self - calibration done . 1: s elects i dac self - calibration. 3 calclk 0 (default): calibration clock disab led . 1: c alibrates clock enabled. 2:0 divsel[2:0] calibration clock divide ratio from dac clock rate . 000 (default): divide by 256 . 001: divide by 128 . ? 110: divide by 4 . 111: divide by 2. cal memory 0x0f 7 calstatq 0 (default): q dac calibration in progress . 1: calibration of q dac complete . 6 calstati 0 (default): i dac calibration in progress . 1: calibration of i dac complete . 3:2 calmemq[1:0] status of q dac calibration memory . 00 (default): u ncal ibrated. 01: s elf - calibrated. 10: user - calibrated. 1:0 calmemi[1:0] status of i dac calibration memory . 00 (default): u ncalibrated. 01: s elf - calibrated. 10: u ser - calibrated. memory address 0x10 5:0 memaddr[5:0] address of stat ic memory to be accessed . memory data 0x11 5:0 memdata[5:0] data for static memory access .
data sheet ad9114/ad9115/ad9116/ad9117 rev. d | page 39 of 52 register address bit name description memory r/w 0x12 7 calrstq 0 (default): n o action . 1: clears calstatq. 6 calrsti 0 (default): n o action . 1: clears calstati. 4 calen 0 (default): no action . 1: initiates device self - calibration. 3 smemwr 0 (default): n o action . 1: writes to static memory (calibration coefficients). 2 smemrd 0 (default): n o action . 1: reads from static memory (calibration coefficients). 1 uncalq 0 (default): n o action . 1: resets q dac calibration coefficients to default (uncalibrated). 0 uncali 0 (default): n o action . 1: resets i dac calibration coefficients to default (uncalibrated). clkmode 0x14 7:6 clkmodeq[1:0] depending on clkm oden bit setting, these two bits reflect the phase relationship between dclkio and clkin , as described in table 16 . if clkmoden = 0, read only; reports the clock phase chosen by the retim e. if clkmoden = 1, read/write; value in this register sets q clock phases; force if needed to better synchronize the dacs (see the retimer section). 4 searching data path retimer status bit . 0 (default): clock relationship established. 1: indicates that the internal datapath retimer is searching for clock relationship (device output is not usable while this bit is high). 3 reacquire edge triggered, 0 to 1 causes the retimer to reacquire the clock relations hip . 2 clkmoden 0 (default): clkmodei/ clkmode q values computed by the two retimers and read back in clkmodei[1:0] and clkmodeq[1:0] . 1: clkmode values set in clkmodei[1:0] override both i and q retimers. 1:0 clkmodei[1:0] depending on clkmoden bit settin g, these two bits reflect the phase relationship between dclkio and clkin, as described in table 16 . if clkmoden = 0, read only; reports the clock phase chosen by the retim e r. if clkmoden = 1, read/write; value in this register sets i clock phases; force if needed to better synchronize the dacs (see the retimer section). version 0x1f 7:0 version [7:0] hardware version of the device . this register is set to 0x0 a fo r the latest version of the device.
ad9114/ad9115/ad9116/ad9117 data sheet rev. d | page 40 of 52 digital interface operation digital data for the i and q dacs is supplied over a single parallel bus (db[n:0], where n is 7 for the ad9114, is 9 for the ad9115, is 11 for the ad9116, and 13 for the ad9117) accompanied by a qualifying clock (dclkio). the i and q data are provided to the chip in an interleaved double data rate (ddr) format. the maximum guaranteed data rate is 250 msps with a 125 mhz clock. the order of data pairing and the sampling edge selection is user programmable using the ifirst and irising data control bits, resulting in four possible timing diagrams. these timing diagrams are shown in figure 89, figure 90, figure 91, and figure 92. dclkio notes: 1. db[n:0], where n is 7 for the ad9114, 9 for the ad9115, 11 for the ad9116, and 13 for the ad9117. db[n:0] z a b c d e f g h i data z b d f q data y a c e 07466-051 figure 89. timing diagram with ifirst = 0, irising = 0 dclkio za b c d e f g h i data y a c e q data x z b d 07466-052 notes: 1. db[n:0], where n is 7 for the ad9114, 9 for the ad9115, 11 for the ad9116, and 13 for the ad9117. db[n:0] figure 90. timing diagram with ifirst = 0, irising = 1 dclkio za b c d e f g h i data z b d f q data a c e g 07466-053 notes: 1. db[n:0], where n is 7 for the ad9114, 9 for the ad9115, 11 for the ad9116, and 13 for the ad9117. db[n:0] figure 91. timing diagram with ifirst = 1, irising = 0 dclkio za b c d e f g h i data y a c e q data z b d f 07466-054 notes: 1. db[n:0], where n is 7 for the ad9114, 9 for the ad9115, 11 for the ad9116, and 13 for the ad9117. db[n:0] figure 92. timing diagram with ifirst = 1, irising = 1 ideally, the rising and falling edges of the clock fall in the center of the keep-in window formed by the setup and hold times, t s and t h . refer to table 2 for setup and hold times. a detailed timing diagram is shown in figure 93. dclkio db[n:0] t s t h t s t h 07466-055 notes: 1. db[n:0], where n is 7 for the ad9114, 9 for the ad9115, 11 for the ad9116, and 13 for the ad9117. figure 93. setup and hold times for all input modes in addition to the different timing modes listed in table 2, the input data can also be presented to the device in either unsigned binary or twos complement format. the format type is chosen via the twos data control bit.
data sheet ad9114/ad9115/ad9116/ad9117 rev. d | page 41 of 52 4 3 2 0 d-ff d-ff 5 d-ff d-ff d-ff or dclkio-int clkin-int db[n:0] (input) to dac core i out i out delay1 delay2 delay1 retimer-clk ie ie oe dclkio (input/output) clkin (input) notes d-ffs: 0: rising or falling edge triggered for i or q data. 1, 2, 3, 4: rising edge triggered. retimer-clk 07466-056 1 d-ff figure 94. simplified diagram of ad9114/ad9115/ad9116/ad9117 timing digital data latching and retimer section the ad9114/ad9115/ad9116/ad9117 have two clock inputs, dclkio and clkin. the clkin is the analog clock whose jitter affects dac performance, and the dclkio is a digital clock from an fpga that needs to have a fixed relationship with the input data to ensure that the data is sampled correctly by the flip-flops on the pads. figure 94 is a simplified diagram of the entire data capture system in the ad9114/ad9115/ad9116/ad9117. the double data rate input data (db[n:0], where n is 7 for the ad9114, is 9 for the ad9115, is 11 for the ad9116, and 13 for the ad9117) is latched at the pads/pins either on the rising edge or the falling edge of the dclkio-int clock, as determined by irising, bit 4 of spi address 0x02. bit 5 of spi address 0x02, ifirst, determines which channel data is latched first (that is, i or q). the captured data is then retimed to the internal clock (clkin-int) in the retimer block before being sent to the final analog dac core (d-ff 4), which controls the current steering output switches. all delay blocks depicted in figure 94 are non-inverting, and any wires without an explicit delay block can be assumed to have no delay. only one channel is shown in figure 94 with the data pads (db[n:0], where n is 7 for the ad9114, is 9 for the ad9115, is 11 for the ad9116, and 13 for the ad9117) serving as double data rate pads for both channels. the default pinmd and spi settings are ie = high (closed) and oe = low (open). these settings are enabled when reset/pinmd (pin 35) is held high. in this mode, the user has to supply both dclkio and clkin. in pinmd, it is also recommended that the dclkio and the clkin be in phase for proper functioning of the dac, which can easily be ensured by tying the pins together on the pcb. if the user can access the spi, setting bit 2 of spi address 0x02, dci_en, to logic low causes the clkin to be used as the dclkio also. setting bit 1 or bit 0 of spi address 0x02, dcosgl or dcodbl, to logic high allows the user to get a dclkio output from the clkin input for use in the users pcb system. it is strongly recommended that dci_en = dcosgl = high, or dci_en = dcodbl = high not be used, even though the device may appear to function correctly. similarly, dcosgl and dcodbl should not be set to logic high simultaneously. retimer the ad9114/ad9115/ad9116/ad9117 ha ve an internal data retimer circuit that compares the clkin-int and dclkio-int clocks and, depending on their phase relationship, selects a retimer clock (retimer-clk) to safely transfer data from the dclkio used at the chips input interface to the clkin used to clock the analog dac cores (d-ff 4). the retimer selects one of the three phases shown in figure 95. the retimer is controlled by the clkmode spi bits as is shown in table 15. 1/2 period 1/4 period 1/2 period data clock retimer-clks 18090 270 07466-057 figure 95. retimer-clk phases note that, in most cases, more than one retimer phase works and, in such cases, the retimer arbitrarily picks one phase that works. the retimer cannot pick the best or safest phase. if the user has a working knowledge of the exact phase relationship between dclkio and clkin (and thus dclkio-int and clkin-int because the delay is approximately the same for both clocks and equal to delay1), then the retimer can be forced to this phase with clkmoden = 1, as described in table 15 and the following paragraphs.
ad9114/ad9115/ad9116/ad9117 data sheet rev. d | page 42 of 52 table 15 . timer r egister list bit name description clkmodeq[1:0] q datapath retimer clock selected output. valid after the searching bit goes low. searching high indicates that the internal datapath retimer is searching for the clock relationship (dac is not usable until it is low again). reacquire changing this bit from 0 to 1 causes the datapath retimer circuit to reacquire the clock rela tionship. clkmode n 0: uses the clkmodei/clkmodeq values (as computed by the two internal retimers) for i and q clocking. 1 : uses the clkmode value set in clkmodei[1:0] to override the bits fo r both the i and q retimers (that is, force the retimer). clkmodei[1:0] i datapath retimer clock selected output. valid after searching goes low. if clkmoden = 1, a value written to this register overrides both i and q automatic retimer values. table 16 . clkmode i/clkmodeq details clkmodei [1:0]/clkmodeq[1:0] dclkio - to - clkin phase relationship retimer - clk selected 00 0 to 90 phase 2 01 90 to 180 phase 3 10 180 to 270 phase 3 11 270 to 360 phase 1 when reset is pulsed high and then returns low ( the part is in spi mode), the retimer runs and automatically selects a suitable clock phase for the retimer - clk within 128 clock cycles. the spi searching bit , b it 4 of spi address 0x14, returns to low , indicat ing that the retimer has locked and the part is ready for use. the reacquire bit, bi t 3 of spi address 0x14, can be used to reinitiate phase detection in the i and q retimers at a ny time. clkmodeq[1:0] and clkmodei[1:0] bits of spi address 0x14 provide readback for the values picked by the internal phase detectors in the retimer (see table 16 ). to force the two retimers (i and q) to pick a particular phase for t he retimer clock (they must both be forced to the same v alue), clkmoden , b it 2 of the spi a ddress 0x14 , should be set high and the required phase value is written into clkmodei[1:0]. for example, if the dclkio and the clkin are in phase to first order, the user could safely force the retimers to pick phase 2 for the retimer - clk. this forcing function may be useful for synchronizing multiple devices. in pin mode , it is expected that the user tie clkin and dclkio together. t he device has a small amount of pr ogrammable func - tionality using the now unused spi pins (sclk, sdio, and cs ). if the two chip clocks are tied together , the sclk pin can be tied to ground , and the chip uses a clock for the retimer that is 180 out of phase with the two i nput clocks (that is, phase 2, which is the safest and best option). the chip has an additional option in pin mode when the redefined sclk pin is high. use this mode if u s ing pin mode , but clkin and dclkio are not tied together (that is, not in phase ). hol ding sclk high causes the internal clock detector to use the phase detector output to determine which clock to use in the retimer (tha t is, select a suitable retimer - clk phase). t he action of taking sclk high causes the internal phase detector to reexamine the two clocks and determine the relative phase. whenever the user wants to reevaluate the relative phase of the two clocks , the sclk pin can be taken low and then high again. estimating the overa ll dac pipeline dela y dac pipeline latency is affec ted by the phase of the retimer - clk that is selected. if latency is critical to the syste m and must be constant, the retimer should be forced to a particular phase and not be allowed to automatically select a phase each time. consider the case in which dclkio = clkin (that is, in phase), and the retimer - clk is forced to phase 2. assume that irising is 1 (that is, i data is latched on the rising edge and q data is latched on the falling edge). then the latency to the output for the i channel is four clock cycles t otal; one clock cycle from the input interface (d - ff 1, not d - ff0 as it latches data on either edge and does not cause any delay), two clock cycles from the retimer (d - ff 2 and d - ff 4, but not d - ff 3 because it is latched on the half clock cycle or 180), and one clock cycle going through the analog core (d - ff 5). the latency to the output for the q channel from the time the falling edge latches it at the pads in d - ff 0 is 3.5 clock cycles (no delay due to d - ff0, 1 clock cycle due to d - ff 1, ? clock cycle t o d - ff 2, 1 clock cycle to d- ff 4, and 1 clock cycle to d - ff 5). this latency for the ad9714/ ad9715/ad9716/ad9717 is case specific and needs to be calcu - lated based on the retimer - clk phase that is automatically selected or manually forced.
data sheet ad9114/ad9115/ad9116/ad9117 rev. d | page 43 of 52 r efe rence o peration the ad9114/ad9115/ad9116/ad9117 contains an internal 1.0 v band gap reference. the internal reference can be disabled by setting b it 0 (extref) of the power - down register (a ddress 0x01) through the spi interface . to use the internal referen ce, decouple the refio pin to a vss with a 0.1 f capacitor, enable the internal reference, and clear b it 0 of the power - down register (a ddress 0x01) through the spi interface. note that this is the default configuration. the internal reference voltage is present at refio. if the voltage at refio is to be used anywhere else in the circuit, an external buffer amplifier with an input bias cur rent of less than 100 na must be used to avoid loading the reference. an example of the use of the internal reference is shown in figure 96 . current scaling x32 ad9114/ad9115/ ad9116/ad9117 i dac or q dac 07466-218 i xoutfs xr set 0.1f refio i xref avss fsadjx v bg 1.0v + C figure 96 . internal reference configuration refio serves as either an input or an output, depending on whether the internal or an external reference is used. table 17 summarizes the reference operation. table 17 . reference o peration reference mode refio p in register s etting internal connect 0.1 f capacitor register 0x01, bit 0 = 0 (default) external apply external r eference registe r 0x01, bit 0 = 1 (for power saving) an external reference can be used in applications requiri ng tighter gain tolerances or lower temperature drift. in addition , a variable external voltage reference can be used to implement a method for gain control of t he dac output. recommendations w hen u sing an external reference apply the external reference to the refio pin . the internal reference can be directly overdriven by the external reference, or the internal reference can be powered down to save power consump tion . the external 0.1 f compensation capacitor on refio is not required unless specified by the external voltage reference manufacturer . the input impedance of refio is 10 k when the internal reference is powered up and 1 m when it is powered down. reference control a mplifier the ad9114/ad9115/ad9116/ad9117 contains a control amplifier that regulates the full - scale output current, i xo utfs . the control amplifier is configured as a v - i converter, as shown in figure 96. the output current, i x ref , is determined by the ratio of the v refio and an external resistor, xr set , as stated in equation 4 (se e the dac transfer function section) . i xref is mirrored to the segmented current sources with the proper scale factor to set i xoutfs , as stated in equation 3 (see the dac tr ansfer function section) . the control amplifier allows a 10 :1 adjustment span of i xoutfs from 2 ma to 20 ma by setting i xref between 62.5 a and 625 a (xr set between 1.6 k? and 16 k? ). when using a resistor larger than 4 k?, split the resistor with 4 k? plus the additional resistance needed , for example, 16 k? made of a 4 k? + 12 k? combination, and add a 1 f cap acitor from 4 k ? to grou nd . the wide adjustment span of i xoutfs provides several benefits. the first relates directly to the power dissipation of the ad9114/ad9115/ad9116/ad9117 , which is proportional to i xoutfs (see the dac transfer function section). the second benefit relates to the ability to adjust the output over a 8 db range with 0.25 db steps , whi ch is useful for controlling the transmitted power. the small signal bandwidth of the reference control amplifier is approximately 500 khz. this allows the device to be used for low frequency, small signal multiplying applications. dac t ransfer f unction th e ad9114/ad9115/ad9116/ad9117 provides two differential current outputs, ioutp/ iout n and qoutp/ qout n. ioutp and qoutp provide a near full - scale current output, i xoutfs , when all bits are high (that is, dac code = 2 n ? 1, where n = 8, 10, 12, or 14 for the ad9114, ad9115, ad9116, and ad9117, respectively), while ioutn and qoutn, the complementary outputs, provide no current. the current output s appearing at the positive dac outputs, ioutp and qoutp, and at the negative dac outputs, ioutn and qoutn, are a fu nction of both the input code and i xoutfs and can be expressed as follows: ioutp = ( idac code /2 n ) i i outfs (1) qoutp = ( qdac code /2 n ) i qoutfs ioutn = ((2 n ? 1) ? idac code )/2 n i ioutfs (2) qoutn = ((2 n ? 1) ? qdac code )/2 n i qoutfs where: idac code and qdac code = 0 to 2 n ? 1 (that is, decimal representation). i io utfs and i qo utfs are function s of the reference current s , i ir ef and i qr ef , respectively , whi ch are nominally set by a reference voltage, v refio , and external resistor s, ir set and q r set , respectively . i ioutfs and i qoutfs can be expressed as follows: i io utfs = 32 i ir ef (3) i qoutfs = 32 i qref
ad9114/ad9115/ad9116/ad9117 data sheet rev. d | page 44 of 52 where: i ir ef = v refio / ir s et (4) i qref = v refio /qr s et or i ioutfs = 32 v refio / ir set (5) i qoutfs = 32 v refio / qr set a differential pair (ioutp/ iout n or qoutp/ qout n) typically drive s a resistive load directly or via a transformer. if dc coupling is required, the differential pair ( ioutp / iout n or q out p/ qout n) should be connected to matching resistive loads, xr load , that are tied to analog common, a vss . the single - ended voltage output appearing at the positive and negative nodes is v ioutp = ioutp ir load (6 ) v qoutp = qoutp qr load v ioutn = ioutn ir lo ad (7) v qoutn = qoutn qr load to achieve the maximum output compliance of 1 v at the nominal 20 ma output current, ir lo ad = qr load must be set to 5 0 . substituting the values of ioutp, ioutn, i xref , and v id iff can be expressed as v idiff = {(2 i dac code ? (2 n ? 1))/2 n } (32 v refio / ir set ) ir load (8) equation 8 h ighlight s some of the advantages of operating the ad9114/ad9115/ad9116/ad9117 diff erentially. first, the differential operation helps cancel common - mode error sources associated with ioutp and ioutn, such as noise, distortion, and dc offsets . second, the differential code - dependent current and subsequent voltage, v idiff , is twice the va lue of the single - ended voltage output (that is, v ioutp or v ioutb ), thus providing twice the signal power to the load. note that the gain drift tempera ture performance for a single - ended output (v ioutp and v ioutn ) or differential output of the ad9114/ad911 5/ad9116/ ad9117 can be enhanced by selecting temperature tracking resistors for xr load and xr set b ecause of their ratio metric relationship, as shown in equation 8. analog o utput the complementary current outputs in each dac, ioutp/ iout n and qoutp/ qout n, can be configured for single - ended or differential operation. ioutp/ iout n and qoutp/ qout n can be converted into complementary single - ended voltage outputs, v ioutp and v ioutn as well as v qoutp and v qoutn via a load resistor, xr load , as described in the dac transfer function section by equation 6 through equation 8 . the differential voltages, v idiff and v qdiff , existing between v ioutp and v ioutn , and v qoutp and v qoutn , can also be converted to a single - ended voltage via a transformer or a differential amplifier configuration. the ac performance of the ad9114/ad9115/ad9116/ ad9117 is optimum and is specified using a differential transformer - coupled output in which the voltage swing at ioutp and ioutn is limited to 0.5 v. the distortion and noise performance of the ad9114/ad9115/ad9116/ad9117 can be enhanced when it is configured for differen tial operation. the common - mode error sources of both ioutp/ iout n and qoutp/ qout n can be significantly reduced by the common - mode r ejection of a transformer or differential amplifier. these common - mode error sources include even - order distortion products and noise. the enhancement in distortion performance becomes more significant as the frequency content of the reconstructed wavefor m increases and/or its amplitude incr eases. this is due to the first - order cancellation of various dynamic common - mode distortion mechanisms, digital feedthrough, and noise. performing a differential - to -single- ended conversion via a transformer also provid es the ability to deliver twice the reconstructed signal power to the load (assuming no source termination). because the output currents of ioutp/ iout n and qoutp/ qout n are complementary, they become additive when processed differentially. s elf - calibration the ad 9114/ad9115/ad9116/ad9117 have a self - calibration feature that improves the dnl of the device. performing a self - calibration on the device improves device performance in low frequency applications. the device performance in applications where the ana log output frequencies are above 5 mhz are generally influenced more by dynamic device behavior than by dnl and , in these cases, self - calibration is unlikely to pro duce measurable benefits . the calibration clock frequency is equal to the dac cloc k divided by the division factor chosen by the divsel value . there is a fixed pre - divider of 16 and it is multiplied by the divsel , which has a range of divide by 2 - 256. each calibr ation clock cycle is between 32 and 2048 dac input clock cycles, depen ding on the va lue of divsel[2:0] (register 0x0e, bits[2:0]) . the frequency of the calibration clock should be between 0.5 mhz and 4 mhz for reliable calibrations. best results are obtained by setting divsel[2:0] to produce a calibration clock frequency between these values. separate self - calibration hardware is included for each dac. the dacs can be self - calibrated individually or simultaneously. to perform a device self - calibration, use the f ollowing procedure: 1. write 0x00 to register 0x12. this e nsures that the u n cali a nd uncalq bits (bit 1 and bit 0) are reset. 2. set up a calibration clock between 0.5 mhz and 4 mhz using divsel[2:0] , and then enable the calibration clock by setting the calclk bit (register 0x0e, bit 3). 3. select the dac(s) to self - calibrate by setting eit her bit 4 (calseli) for the i dac and/or bit 5 (calselq) for the q dac in register 0x0e. note that each dac contains independent calibration hardware so that they can be calibrated simultaneously. 4. start self - calibration by setting bit 4 (calen) in regist er 0x12 . wait approximately 300 calibration clock cycles.
data sheet ad9114/ad9115/ad9116/ad9117 rev. d | page 45 of 52 5. check if the self-calibration has completed by reading bit 6 (calstati) and bit 7 (calstatq) in register 0x0f. logic 1 indicates that the calibration has completed. 6. when the self-calibration has completed, write 0x00 to register 0x12. 7. disable the calibration clock by clearing bit 3 (calclk) in register 0x0e. the ad9114/ad9115/ad9116/ad9117 allow reading and writing of the calibration coefficients. there are 32 coefficients in total. the read/write feature of the coefficients can be useful for improving the results of the self-calibration routine by averaging the results of several self-calibration cycles and loading the averaged results back into the device. to read the calibration coefficients, use the following steps: 1. select which dac core to read by setting either bit 4 (calseli) for the i dac or bit 5 (calselq) for the q dac in register 0x0e. write the address of the first coefficient (0x01) to register 0x10. 2. set bit 2 (smemrd) in register 0x12 by writing 0x04 to register 0x12. 3. read the 6-bit value of the first coefficient by reading the contents of register 0x11. 4. clear the smemrd bit by writing 0x00 to register 0x12. 5. repeat step 2 through step 4 for each of the remaining 31 coefficients by incrementing the address by 1 for each read. 6. deselect the dac core by clearing either bit 4 (calseli) for the i dac and/or bit 5 (calselq) for the q dac in register 0x0e. to write the calibration coefficients to the device, use the following steps: 1. select which dac core to write to by setting either bit 4 (calseli) for the i dac or bit 5 (calselq) for the q dac in register 0x0e. 2. set bit 3 (smemwr) in register 0x12 by writing 0x08 to register 0x12. 3. write the address of the first coefficient (0x01) to register 0x10. 4. write the value of the first coefficient to register 0x11. 5. repeat step 2 through step 4 for each of the remaining 31 coefficients by incrementing the address by one for each write. 6. clear the smemwr bit by writing 0x00 to register 0x12. 7. deselect the dac core by clearing either bit 4 (calseli) for the i dac or bit 5 (calselq) for the q dac in register 0x0e. coarse gain adjustment option 1 a coarse full-scale output current adjustment can be achieved using the lower six bits in register 0x0d. this adds or subtracts up to 20% from the band gap voltage on pin 34 (refio), and the voltage on the fsadjx resistors tracks this change. as a result, the dac full-scale current varies by the same amount. a secondary effect to changing the refio voltage is that the full-scale voltage in the auxdac also changes by the same magnitude. the register uses twos complement format, in which 011111 maximizes the voltage on the refio node and 100000 minimizes the voltage. 1.30 1.25 1.20 1.15 1.10 1.05 1.00 0.95 0.90 0.85 0.80 0 8 16 24 32 40 48 56 code v ref (v) 07466-058 figure 97. typical v ref voltage vs. code option 2 while using the internal fsadjx resistors, each main dac can achieve independently controlled coarse gain using the lower six bits of register 0x04 (irset[5:0 ]) and register 0x07 (qrset[5:0]). unlike coarse gain option 1, this impacts only the main dac full-scale output current. the register uses twos complement format and allows the output current to be changed in approximately 0.25 db steps. 2018 2216 10 12 14 86 4 2 0 1 02 03 04 05 06 0 xr set code i f (ma) v out_q or v out_i 07466-059 figure 98. effect of xr set code option 3 even when the device is in pin mode, full-scale values can be adjusted by sourcing or sinking current from the fsadjx pins. any noise injected here appears as amplitude modulation of the output. thus, a portion of the required series resistance (at least 20 k) must be installed right at the pin. a range of 10% is quite practical using this method. option 4 as in option 3, when the device is in pin mode, both full-scale values can be adjusted by sourcing or sinking current from the
ad9114/ad9115/ad9116/ad9117 data sheet rev. d | page 46 of 52 refio pin. noise injected here appears as amplitude modulation of the output; therefore, a portion of the required series resistance (at least 10 k) must be installed at the pin. a range of 25% is quite practical when using this method. fine gain each main dac has independent fine gain control using the lower six bits in register 0x03 (i dacgain[5:0]) and register 0x06 (q dacgain[5:0]). unlike coarse gain option 1, this impacts only the main dac full-scale output current. these registers use straight binary format. one application in which straight binary format is critical is for side-band suppression while using a quadrature modulator. this is described in more detail in the applications information section. 11.10 11.00 10.90 10.80 10.70 10.60 10.50 0 8 16 24 32 40 48 56 64 gain dac code i outfs (ma) 3.3v dac1 3.3v dac2 1.8v dac1 1.8v dac2 0 7466-060 figure 99. typical dac gain characteristics using the internal termination resistors the ad9117/ad9116/ad9115/ad9114 have four 62.5 termination internal resistors (two for each dac output). to use these resistors to convert the dac output current to a voltage, connect each dac output pin to the adjacent load pin. for example, on the i dac, ioutp must be shorted to rlip and ioutn must be shorted to rlin. in addition, the cmli or cmlq pin must be connected to ground directly or through a resistor. if the output current is at the nominal 20 ma and the cmli or cmlq pin is tied directly to ground, this produces a dc common-mode bias voltage on the dac output equal to 0.625 v. if the dac dc bias must be higher than 0.625 v, an external resistor can be connected between the cmli or cmlq pin and ground. this part also has an internal common-mode resistor that can be enabled. this is explained in the using the internal common-mode resistor section. i dac or q dac xr cm cml rlin ioutn ioutp rlip 62.5 ? 62.5 ? 07466-061 figure 100. simplified internal load options using the internal common-mode resistor these devices contain an adjustable internal common-mode resistor that can be used to increase the dc bias of the dac outputs. by default, the common-mode resistor is not connected. when enabled, it can be adjusted from ~60 to ~260 . each main dac has an independent adjustment using the lower six bits in register 0x05 (ircml[5:0]) and register 0x08 (qrcml[5:0]). 260 220 240 200 180 160 140 120 100 8060 0 8 16 24 32 40 48 56 code resistance ( ? ) 07466-062 figure 101. typical cml resistor value vs. register code using the cmlx pins for optimal performance the cmlx pins also serve to change the dac bias voltages in the parts allowing them to run at higher dc output bias voltages. when running the bias voltage below 0.9 v and an avdd of 3.3 v, the parts perform optimally when the cmlx pins are tied to ground. when the dc bias increases above 0.9 v, set the cmlx pins at 0.5 v for optimal performance. the maximum dc bias on the dac output should be kept at or below 1.2 v when the supply is 3.3 v. when the supply is 1.8 v, keep the dc bias close to 0 v and connect the cmlx pins directly to ground.
data sheet ad9114/ad9115/ad9116/ad9117 rev. d | page 47 of 52 applications information output configurations the following sections illustrate some typical output configu- rations for the ad9114/ad9115/ad9116/ad9117. unless otherwise noted, it is assumed that i xoutfs is set to a nominal 20 ma. for applications requiring the optimum dynamic performance, a differential output configuration is suggested. a differential output configuration can consist of either an rf transformer or a differential op amp configuration. the trans- former configuration provides the optimum high frequency performance and is recommended for any application that allows ac coupling. the differential op amp configuration is suitable for applications requiring dc coupling, signal gain, and/or a low output impedance. a single-ended output is suitable for applications in which low cost and low power consumption are primary concerns. differential coupling using a transformer an rf transformer can be used to perform a differential-to- single-ended signal conversion, as shown in figure 102. the distortion performance of a transformer typically exceeds that available from standard op amps, particularly at higher frequencies. transformer coupling provides excellent rejection of common-mode distortion (that is, even-order harmonics) over a wide frequency range. it also provides electrical isolation and can deliver voltage gain without adding noise. transformers with different impedance ratios can also be used for impedance matching purposes. the main disadvantages of transformer coupling are low frequency roll-off, lack of power gain, and high output impedance. ad9114/ad9115/ ad9116/ad9117 ioutn ioutp 29 28 optional r diff r load 07466-063 figure 102. differential output using a transformer the center tap on the primary side of the transformer must be connected to a voltage that keeps the voltages on ioutp and ioutn within the output common-mode voltage range of the device. note that the dc component of the dac output current is equal to i ioutfs and flows out of both ioutp and ioutn. the center tap of the transformer should provide a path for this dc current. in most applications, agnd provides the most convenient voltage for the transformer center tap. the comple- mentary voltages appearing at ioutp and ioutn (that is, v ioutp and v ioutn ) swing symmetrically around agnd and should be maintained with the specified output compliance range of the ad9114/ad9115/ad9116/ad9117. a differential resistor, r diff , can be inserted in applications in which the output of the transformer is connected to the load, r load , via a passive reconstruction filter or cable. r diff , as reflected by the transformer, is chosen to provide a source termination that results in a low voltage standing wave ratio (vswr). note that approximately half the signal power is dissipated across r diff . single-ended buffered output using an op amp an op amp, such as the ada4899-1 , can be used to perform a single- ended current-to-voltage conversion, as shown in figure 103. figure 103 is a simplified schematic. the refio pin must be buffered to keep the load current less than 100 na. the ad9114/ ad9115/ad9116/ad9117 are configured with a pair of series resistors, r s , off each output. for best distortion performance, r s should be set to 0 . the feedback resistor, r fb , determines the peak-to-peak signal swing by the formula v out = r fb i fs the common-mode voltage of the output is determined by the formula 2 1 fs fb b fb ref cm i r r r v v ? ? ?? ? ? ?? ? + = the maximum and minimum voltages out of the amplifier are, respectively, ? ?? ? ? ?? ? + = b fb ref max r r v v 1 v min = v max ? i fs r fb +5v ad9114/ad9115/ ad9116/ad9117 ioutp ioutn 29 r fb v out refio 34 28 r s avss 25 c f c r s r b + C ada4899-1 C5v 07466-064 figure 103. single-suppl y, single-ended buffer
ad9114/ad9115/ad9116/ad9117 data sheet rev. d | page 48 of 52 differential buffere d output using an op amp a dual op amp ( see the circuit shown in figure 104 ) can be used in a differential version of the single - ended buffer shown in figure 103 . figu re 104 is a simplified schematic. the refio pin must be buffered to keep the load current less than 100 na. the same rc network is used to form a one - pole differential, low - pass filter to isolate the op amp inputs from the high frequency images produced b y the dac outputs. the feed back resistors, r fb , determine the differential peak - to - peak signal swing by the formula v out = 2 r fb i fs the maximum and minimum single - ended voltages out of the amplifier are, respectively, ? ?? ? ? ?? ? + = b fb ref max r r v v 1 v min = v max ? r fb i fs the common - mode voltage of the differential output is determined by the formula v cm = v max ? r fb i fs ad9114/ad9115/ ad9116/ad9117 ioutp ioutn r fb v out refio 34 28 r s avss 25 c f c r fb r b c f r s r b 29 + C ada4841-2 + C ada4841-2 07466-065 figure 104 . single - supply differential buffer auxiliary dac s the dacs of the ad 9114/ad9115/ad9116/ad9117 feature two ve rsatile and independent 10 - bit auxiliary dacs suitable for dc offset correction and similar tasks. because the auxdacs are driven through the spi port , they should never be used in timing - critical applications , such as inside analog feedback loop s. to keep the pin count reasonable , these auxiliary dacs each share a pin with the corresponding fsadj x resistor. they are , therefore , usable only when enabled and when that dac is operated on its internal full - scale resistors. a simple i - to - v converter is implemented on - chip with selectable shunt resistors (3. 2 k to 16 k ) such that if re fio is set to exactly 1 v , refio/2 e quals 0.5 v and the following equation describe s the no load output voltage: k 16 5.1 v5.0 ? ?? ? ? ?? ? ? ? = s dac out r i v figure 105 illustrates the function of all the spi bits controlling these dacs with the exception of the qauxen (register 0x0a) and iauxen (register 0x0c) bits and gating to prohibit r s < 3.2 k . + C op amp auxdac [9:0] a vdd rng0 rng1 refio 2 16k? 16k? 16k? 4k? 8k? ofs2 ofs1 ofs0 (ofs > 4 = 4) aux pin rng: 00 = 125 a f s 01 = 62 a f s 10 = 31 a f s 1 1 = 16 a f s 07466-066 figure 105 . aux dac s implified circuit diagram the spi speed limits the update rate of the auxiliary dacs. the data is inverted such that i auxdac is full scale at 0x 000 and zero at 0x1ff , as shown in figure 106 . 3.0 2.8 2.6 2.4 2.2 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 0 10 20 30 40 50 60 70 80 90 100 120 130 dac current (a) output (v) 110 r offset = 3.3k? r offset = 4k? r offset = 5.3k? r offset = 8k? r offset = 16k? op am p output vo lt age vs. changes in r offset and dac current in a 07466-067 figure 106 . auxdac op amp output vs. current, avdd = 3.3 v no load , auxdac 0x 1ff to 0x 000
data sheet ad9114/ad9115/ad9116/ad9117 rev. d | page 49 of 52 two registers are assigned to each dac with 10 bits for the actual dac current to be generated, a 3-bit offset (and gain) adjustment, a 2-bit current range adjustment, and an enable/ disable bit. setting the qauxofs (register 0x0a) and iauxofs (register 0x0c) bits to all 1s disables the respective op amp and routes the dac current directly to the respective fsadji/auxi or fsadjq/auxq pins. this is especially useful when the loads to be driven are beyond the limited capability of the on-chip amplifier. when not enabled (qauxen or iauxen = 0), the respective dac output is in open circuit. dac-to-modulator interfacing the auxiliary dacs can be used for local oscillator (lo) cancellation when the dac output is followed by a quadrature modulator. this lo feedthrough is caused by the input referred dc offset voltage of the quadrature modulator (and the dac output offset voltage mismatch) and can degrade system performance. typical dac-to-quadrature modulator interfaces are shown in figure 107 and figure 108, with the series resistor value chosen to give an appropriate adjustment range. figure 107 also shows external load resistors in use. often, the input common- mode voltage for the modulator is much higher than the output compliance range of the dac, so that ac coupling or a dc level shift is necessary. if the required common-mode input voltage on the quadrature modulator matches that of the dac, the dc blocking capacitors in figure 107 can be removed and the on-chip resistors can be connected. ad9114/ad9115/ ad9116/ad9117 auxdac1 ad9114/ad9115/ ad9116/ad9117 i dac 5k ? to 100k ? 50 ? 50 ? optional passive filtering modulator v+ quadrature modulator i or q inputs 0.1f 0.1f 07466-268 figure 107. typical use of auxiliary dacs figure 108 shows a greatly simplified circuit that takes full advantage of the internal components supplied in the dac. a low-pass or band-pass passive filter is recommended when spurious signals from the dac (distortion and dac images) at the quadrature modulator inputs can affect the system performance. in the example shown in figure 108, the filter must be able to pass dc to properly bias the modulator. placing the filter at the location shown in figure 107 and figure 108 allows easy design of the filter, because the source and load impedances can easily be designed close to 50 for a 20 ma full-scale output. when the resistance at the modulator inputs is known, an optimum value for the series resistor can be calculated from the modulator input offset voltage ratings. ad9114/ad9115/ ad9116/ad9117 auxdac ad9114/ad9115/ ad9116/ad9117 i or q dac 5k ? 50 ? 50 ? 100 ? optional low- pass filtering adl5370 family i or q inputs 07466-269 figure 108. typical use of auxiliary dacs when dc coupling to quadrature modulator adl537x family correcting for nonideal performance of quadrature modulators on the if-to-rf conversion analog quadrature modulators make it very easy to realize single sideband radios. these dacs are most often used to make radio transmitters, such as in cell phone towers. however, there are several nonideal aspects of quadrature modulator performance. among these analog degradations are gain mismatch and lo feedthrough. gain mismatch the gain in the real and imaginary signal paths of the quadrature modulator may not be matched perfectly. this leads to less than optimal image rejection because the cancellation of the negative frequency image is less than perfect. lo feedthrough the quadrature modulator has a finite dc referred offset, as well as coupling from its lo port to the signal inputs. these can lead to a significant spectral spur at the frequency of the quadrature modulator lo. the ad9114/ad9115/ad9116/ad9117 have the capability to correct for both of these analog degradations. however, understand that these degradations drift over temperature; therefore, if close to optimal single sideband performance is desired, a scheme for sensing these degradations over temperature and correcting them may be necessary. i/q channel gain matching fine gain matching is achieved by adjusting the values in the dac fine gain adjustment registers. for the i dac, these values are in the i dac gain register (register 0x03, i dacgain[5:0]). for the q dac, these values are in the q dac gain register (register 0x06, q dacgain[5:0]). these are 6-bit values that cover 2% of full scale. to perform gain compensation by starting from the default values of zero, raise the value of one of these registers a few steps until it can be determined if the amplitude of the unwanted image is increased or decreased. if the unwanted image increases in amplitude, remove the step and try the same adjustment on the other dac control register. iterate register changes until the rejection cannot be improved further. if the fine gain adjustmen t range is not sufficient to find a null (that is, the register goes full scale with no null apparent), adjust the course gain settings of the two dacs accordingly and try again. variations on this simple method are possible.
ad9114/ad9115/ad9116/ad9117 data sheet rev. d | page 50 of 52 note that lo feedthrough compensation is independent of phase compensation. however, gain compensation can affect the lo compensation because the gain compensation may change the common-mode level of the signal. the dc offset of some modulators is common-mode level dependent. therefore, it is recommended that the gain adjustment be performed prior to lo compensation. lo feedthrough compensation to achieve lo feedthrough compensation in a circuit, each output of the two auxdacs must be connected through a 10 k resistor to one side of the differential dac output. see the auxiliary dacs section for details of how to use auxdacs. the purpose of these connections is to drive a very small amount of current into the nodes at the quadrature modulator inputs, thereby adding a slight dc bias to one or the other of the quadrature modulator signal inputs. to achieve lo feedthrough compensation, the user should start with the default conditions of the auxdac registers and then increment the magnitude of one or the other auxdac output voltages. while this is being done, the amplitude of the lo feedthrough at the quadrature modulator output should be sensed. if the lo feedthrough amplitude increases, try either decreasing the output voltage of the auxdac being adjusted or try adjusting the output voltage of the other auxdac. it may take practice before an effective algorithm is achieved. the ad9114/ad9115/ad9116/ ad9117 evaluation board can be used to adjust the lo feedthrough down to the noise floor, although this is not stable over temperature. results of gain and offset correction the results of gain and offset correction can be seen in figure 109 and figure 110. figure 109 shows the output spectrum of the quadrature demodulator before gain and offset correction. figure 110 shows the output spectrum after correction. the lo feedthrough spur at 450 mhz has been suppressed to the noise level. this result can be achieved by applying the correction, but the correction must be repeated after a large change in temperature. note that gain matching improves the negative frequency image rejection, but it is also related to the phase mismatch in the quadrature modulator. it can be improved by adjusting the relative phase between the two quadrature signals at the digital side or properly designing the low-pass filter between the dacs and quadrature modulators. phase mismatch is frequency dependent; therefore, routines must be developed to adjust it if wideband signals are desired. 5 C5 C15C25 C35 C45 C55 C65 C75 C85 C95 0 C10C20 C30 C40 C50 C60 C70 C80 C90 447.5 449.0 450.0 451.0 452.5 frequency (mhz) db 07466-070 figure 109. ad9114/ad9115/ad9116/ad 9117 and adl5370 with a single- tone signal at 450 mhz, no gain or lo compensation 5 C5 C15 C25 C35 C45 C55 C65 C75 C85 C95 0 C10 C20 C30 C40 C50 C60 C70 C80 C90 447.5 449.0 450.0 451.0 452.5 frequency (mhz) db 07466-071 figure 110. ad9114/ad9115/ad9116/ad 9117 and adl5370 with a single- tone signal at 450 mhz, gain and lo compensation optimized
data sheet ad9114/ad9115/ad9116/ad9117 rev. d | page 51 of 52 outline dimensions 1 40 10 11 31 30 21 20 compliant t o jedec s t andards mo-220-vjjd-2 06-01-2012-d 0.50 bsc pin 1 indic at or 4.50 ref 0.20 min 0.50 0.40 0.30 top view 12 max 0.80 max 0.65 ty p sea ting plane coplanarit y 0.08 1.00 0.85 0.80 0.30 0.23 0.18 0.05 max 0.02 nom 0.20 ref 4.25 4.10 sq 3.95 0.60 max 0.60 max pin 1 indic at or 6.10 6.00 sq 5.90 5.85 5.75 sq 5.65 for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. exposed pad (bottom view) figure 111 . 40 - lead lead frame chip scale package [lfcsp] 6 mm 6 mm and 0.85 mm package height (cp - 40 - 1) dimensions shown in millimeters 10-23-2017-b 0.50 bsc bot t om view top view side view pin 1 indic at or 0.05 max 0.02 nom 0.20 ref coplanarity 0.08 0.30 0.23 0.18 6.10 6.00 sq 5.90 0.80 0.75 0.70 0.45 0.40 0.35 0.20 min 4.25 4.10 sq 3.95 compliant to jedec standards mo-220- wjjd-5 . 40 1 11 20 21 30 31 10 pkg-004354 pin 1 indic at or area options (see detail a) detail a (jedec 95) exposed pad sea ting plane for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. figure 112 . 40 - lead lead frame chip scale package [lfcsp] 6 mm 6 mm and 0.75 mm package height (cp - 40 -9) dimensions shown in millimeters
ad9114/ad9115/ad9116/ad9117 data sheet rev. d | page 52 of 52 ordering guide model 1 temperature range package description package option ad 9114 bcpz ?40c to +85c 40 - lead lfcsp cp - 40 -1 ad 9114 bcpzrl 7 ?40c to +85c 40 - lead lfcsp cp - 40 -1 ad 9115 bcpz ?40c to +85c 40 - lead lfcsp cp - 40 -1 ad 9115 bcpzrl 7 ?40c to +85c 40 - lead lfcsp cp - 40 -1 ad 9116 bcpz ?40c to +85c 40 - lead lfcsp cp - 40 -1 ad 9116 bcpzrl 7 ?40c to +85c 40 - lead lfcsp cp - 40 -1 ad 9117 bcpz ?40c to +8 5c 40 - lead lfcsp cp - 40 -1 ad 9117 bcpzrl 7 ?40c to +85c 40 - lead lfcsp cp - 40 -1 ad9117bcpzn ?40c to +85c 40 - lead lfcsp cp - 40 -9 AD9117BCPZNRL7 ?40c to +85c 40 - lead lfcsp cp - 40 -9 ad 9114 - dpg2 - ebz evaluation board ad 9115 - dpg2 - ebz evaluation board ad 9116 - dpg2 - ebz evaluation board ad 9117 - dpg2 - ebz evaluation board 1 z = rohs compliant part. ? 2008 ? 2017 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d07466 -0- 12/17(d)

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